CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User’s Manual U13850EJ6V0UD
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5.8.1 Interrupt request valid timing after EI instruction
When an interrupt request signal is generated (IF flag = 1) in the status in which the DI instruction is executed
(interrupts disabled) and interrupts are not masked (MK flag = 0), seven system clocks are required from the
execution of the EI instruction (interrupts enabled) to the interrupt request acknowledgment by the CPU. The CPU
does not acknowledge interrupt requests if the DI instruction (interrupts disabled) is executed during the seven
system clocks.
Therefore, seven system clocks worth of instruction execution clocks must be inserted after the EI instruction
(interrupts enabled). However, under the following conditions, interrupt requests cannot be acknowledged even if the
seven system clocks are secured, so securing under the following conditions is prohibited.
•
In IDLE/STOP mode
•
An interrupt request non-sampling instruction (instruction to manipulate the PSW.ID bit) is executed
•
An interrupt request control register (xxICn) is accessed
The following shows an example of program processing.
[Program processing example]
DI
:
; (MK flag = 0)
:
;
←
Interrupt request occurs (IF flag = 1)
EI
; EI instruction executed
NOP
; 1 system clock
NOP
; 1 system clock
NOP
; 1 system clock
NOP
; 1 system clock
JR LP1
; 3 system clocks (branch to LP1 routine)
:
LP1 :
; LPI routine
DI
; After EI instruction execution, NOP instruction is
executed four times, and DI
instruction is executed at the
eighth clock by JR instruction
Note
Do not execute the DI instruction (PSW.ID = 1) during this period.
Remarks 1.
In this example, the DI instruction is executed at the eighth clock after execution of the EI
instruction, so the CPU acknowledges an interrupt request signal and performs interrupt servicing.
2.
The interrupt servicing routine instructions are not executed at the eighth clock after the EI
instruction execution. The interrupt servicing routine instructions are executed four system clocks
after the CPU acknowledges the interrupt request signal.
3.
This example shows the case in which an interrupt request signal is generated (IF flag = 1) before
the EI instruction is executed. If an interrupt request signal is generated after the EI instruction is
executed, the CPU does not acknowledge the interrupt request signal if interrupts are disabled
(PSW.ID = 1) for seven clocks after the IF flag is set (1).
Note
Содержание V850/SB1
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