CHAPTER 10 SERIAL INTERFACE FUNCTION
User’s Manual U13850EJ6V0UD
350
(5) IIC function expansion registers 0, 1 (IICX0, IICX1)
These registers set the function expansion of I
2
Cn (valid only in high-speed mode).
IICXn is set by an 8-bit or 1-bit memory manipulation instruction. Set the CLXn bit in combination with the
SMCn, DFCn, CLn1, and the CLn0 bits of IIC clock selection register n (IICCLn) and the IICCEn1 and IICCEn0
bits of IIC clock expansion register n (IICCEn) (see
10.4.2 (7) I
2
Cn transfer clock setting method
) (n = 0, 1).
RESET input clears these registers to 00H.
(6) IIC clock expansion registers 0, 1 (IICCE0, IICCE1)
These registers set the transfer clock expansion of I
2
Cn.
IICCEn is set by an 8-bit memory manipulation instruction. Set the IICCEn1 and IICCEn0 bits in combination
with the SMCn, CLn1, and CLn0 bits of IIC clock selection register n (IICCLn) and the CLXn bit of IIC function
expansion register n (IICXn) (see
10.4.2 (7) I
2
Cn transfer clock setting method
) (n = 0, 1).
RESET input clears these registers to 00H.
(7) I
2
Cn transfer clock setting method
The I
2
Cn transfer clock frequency (f
SCL
) is calculated using the following expression (n = 0, 1).
f
SCL
= 1/(m
×
T + t
R
+ t
F
)
m = 12, 24, 48, 36, 54, 44, 86, 172, 132, 198 (see
Table 10-9 Selection Clock Setting
.)
T:
1/f
XX
t
R
:
SCLn rise time
t
F
:
SCLn fall time
For example, the I
2
Cn transfer clock frequency (f
SCL
) when f
XX
= 20 MHz, m = 198, t
R
= 200 ns, and t
F
= 50 ns is
calculated using following expression.
f
SCL
= 1/(198
×
50 ns + 200 ns + 50 ns)
≅
98.5 kHz
After reset: 00H
R/W
Address: FFFFF34AH, FFFFF35AH
7
6
5
4
3
2
1
<0>
IICXn
0
0
0
0
0
0
0
CLXn
(n = 0, 1)
After reset: 00H
R/W
Address: FFFFF34CH, FFFFF35CH
7
6
5
4
3
2
1
0
IICCEn
0
0
0
0
0
0
IICCEn1
IICCEn0
(n = 0, 1)
Содержание V850/SB1
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