CHAPTER 12 DMA FUNCTIONS
User’s Manual U13850EJ6V0UD
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Channel n
DMAS2
DMAS1
DMAS0
TTYPn1
TTYPn0
DMA transfer start factor setting
0
0
INTST1
0
1
INTCSI4
1
0
INTAD
4
x
x
x
1
1
INTTM2
0
0
INTCSI3/INTSR1
0
1
INTCSI4
1
0
INTCSI2
5
x
x
x
1
1
INTTM6
TDIRn
Transfer direction control between peripheral I/Os and internal RAM
Note 3
0
From internal RAM to peripheral I/Os
1
From peripheral I/Os to internal RAM
DSn
Control of transfer data size for DMA transfer
Note 3
0
8-bit transfer
1
16-bit transfer
ENn
Control of DMA transfer enable/disable status
Note 4
0
Disabled
1
Enabled (reset to 0 after DMA transfer is completed)
Notes
1.
TCn (n = 0 to 5) is set to 1 when a specified number of transfers are completed, and is cleared to
0 when a write instruction is executed.
2.
INTIIC0 and INTIIC1 are available only in the Y versions (products with on-chip I
2
C).
3.
Make sure that the transfer format conforms to the peripheral I/O register specifications (access-
enabled data size, read/write, etc.) for the DMA peripheral I/O address register (DIOAn).
4.
After the specified number of transfers are completed, this bit is cleared to 0.
Содержание V850/SB1
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