NEC mPD780344 Series, Руководство пользователя

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470
CHAPTER 25 ELECTRICAL SPECIFICATIONS
User’s Manual U15798EJ2V0UD
(f) I
2
C bus mode
Parameter Symbol Standard Mode High-Speed Mode Unit
MIN. MAX. MIN. MAX.
SCL0 clock frequency f
SCL
0 100 0 400 kHz
Bus free time t
BUF
4.7
−
1.3
− µ
s
(between stop and start condition)
Hold time
Note 1
t
HD:STA
4.0
−
0.6
− µ
s
SCL0 clock low-level width t
LOW
4.7
−
1.3
−
µ
s
SCL0 clock high-level width t
HIGH
4.0
−
0.6
− µ
s
Start/restart condition setup time t
SU:STA
4.7
−
0.6
− µ
s
Data hold time CBUS compatible master t
HD:DAT
5.0
− − − µ
s
I
2
C bus 0
Note 2
−
0
Note 2
0.9
Note 3
µ
s
Data setup time t
SU:DAT
250
−
100
Note 4 −
ns
SDA0 and SCL0 signal rise time t
R
−
1,000 20 + 0.1Cb
Note 5
300 ns
SDA0 and SCL0 signal fall time t
F
−
300 20 + 0.1Cb
Note 5
300 ns
Stop condition setup time t
SU:STO
4.0
−
0.6
− µ
s
Capacitive load per each bus line Cb
−
400
−
400 pF
Spike pulse width controlled by input filter t
SP
− −
0 50 ns
Notes 1. On the start condition, the first clock pulse is generated after the hold period.
2. To fulfill the undefined area of the SCL0 falling edge, it is necessary for the device to provide internally
an SDA0 signal (on V
IHmin.
of the SCL0 signal) with at least 300 ns of hold time.
3. If the device does not extend the SCL0 signal low hold time (t
LOW
), only maximum data hold time t
HD:DAT
needs to be fulfilled.
4. The high-speed mode I
2
C bus is available in the standard mode I
2
C bus system. At this time, the
conditions described below must be satisfied.
•
If the device does not extend the SCL0 signal low state hold time
t
SU:DAT
≥
250 ns
•
If the device extends the SCL0 signal low state hold time
Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (t
Rmax.
+
t
SU:DAT
= 1,000 + 250 = 1,250 ns by standard mode I
2
C bus specification).
5. Cb: Total capacitance per bus line (unit: pF)