502
User’s Manual U15798EJ2V0UD
APPENDIX D REVISION HISTORY
The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters
of each edition in which the revision was applied.
(1/4)
Edition
Major Revision from Previous Edition
Applied to:
2nd edition
Deletion of indication “under development” for all target products
Throughout
AV
REF
pin
→
AV
DD
pin
A/D converter operation enable voltage
AV
REF
= 2.7 to 5.5 V
→
AV
DD
= 2.2 to 5.5 V
Change of 113-pin plastic FBGA package in
1.4 Pin Configuration (Top View)
CHAPTER 1 OUTLINE
Modification of
Table 2-1 Pin I/O Circuit Types
CHAPTER 2 PIN FUNCTIONS
Addition of description on program area in
3.1.2 (1) Internal high-speed RAM
CHAPTER 3 CPU
and
(2) Internal expansion RAM
ARCHITECTURE
Change of
Figure 3-10 Data To Be Saved to Stack Memory
and
Figure 3-11
Data To Be Restored from Stack Memory
Modification of
[Description example]
in
3.4.4 Short direct addressing
Addition of
[Illustration]
in
3.4.7 Based addressing, 3.4.8 Based indexed
addressing
, and
3.4.9 Stack addressing
Modification of description of port 1 and port 4 in
Table 4-1 Port Functions
CHAPTER 4 PORT
Modification of
Figure 4-4 P10 to P17 Block Diagram
FUNCTIONS
Addition of
Caution
in
4.2.3 Port 2
Modification of
Note
in
Format of Figure 4-18 Port Mode Registers (PM0,
PM2 to PM4, PM7 to PM11)
Modification of setting and addition of
Caution 2
in
Format of Figure 4-21
Pin Function Switching Registers (PF8 to PF11)
Addition of description in
5.5.1 Main system clock operations
CHAPTER 5 CLOCK
GENERATOR
Modification of
Figure 6-1 Block Diagram of 16-Bit Timer/Event Counter 0
CHAPTER 6 16-BIT TIMER/
Addition of
Figure 6-11 Configuration of
PPG Output
and
Figure 6-12 PPG
EVENT COUNTER 0
Output Operation Timing
Modification of
6.6 (4) Capture register data retention timing
and addition
of
(13) STOP mode and main system clock stop mode settings
Deletion of <1> in
6.6 (7) Conflicting operations
in 1st edition
Modification of Figure
7-6 Format of Carrier Generator Output Control
CHAPTER 7 8-BIT TIMERS
Register B0
A0, B0
Addition of input frequency from TMIB0 pin in
Table 7-7 Square-Wave
Output Range with 16-Bit Resolution
Addition of description in
8.3 (2) 8-bit timer compare register 5n
CHAPTER 8 8-BIT TIMER/
(CR5n: n = 0, 1)
EVENT COUNTERS 50, 51
Addition of
[Setting]
in
8.5.2 External event counter operation
Addition of description on frequencies in
[Setting]
in
8.5.3 Square-wave
output operation
Modification of description of
[Setting]
in
8.5.4 PWM output operation
Содержание mPD780344 Series
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