NEC mPD780344 Series, Руководство пользователя

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CHAPTER 20 STANDBY FUNCTION
User’s Manual U15798EJ2V0UD
20.2 Standby Function Operations
20.2.1 HALT mode
(1) HALT mode setting and operating statuses
The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the
subsystem clock.
The operating statuses in the HALT mode are described below.
Table 20-1. HALT Mode Operating Statuses
HALT Mode During HALT Instruction Execution During HALT Instruction Execution
Setting Using Main System Clock Using Subsystem Clock
Without Subsystem With Subsystem With Main System With Main System
Item Clock
Note 1
Clock
Note 2
Clock Oscillation Clock Oscillation Stopped
Clock generator Both main system clock and subsystem clock can be oscillated. Clock supply to CPU stops.
CPU Operation stops.
Port (output latch) Status before HALT mode setting is held.
×
4 subsystem clock Operation stops.
multiplication circuit
16-bit timer/event Operable Operation stops.
counter 0
8-bit timer A0 Operable Operable when
INTTMB0, carrier
clock, and timer B0 are
selected as count clock
8-bit timer/event Operable Operable when TMIB0
counter B0 is selected as count
clock.
8-bit timer/event Operable Operable when TI50
counters 50, 51 and TI51 are selected
as count clock.
Watch timer Operable when f
X
/2
8
is Operable Operable when f
XT
is
selected as count clock. selected as count clock.
Watchdog timer Operable Operation stops.
Clock output Operable Operable when f
XT
is
selected as count clock.
A/D converter Operation stops.
Serial interface SIO3 Operable Operable with external
Serial interface
SCK.
CSI1
Serial interface Operation stops.
UART0
Serial interface
IIC0
Note 3
LCD controller/driver Operable when f
X
/2
6
Operable Operable when f
XT
is
to f
X
/2
8
is selected as selected as count clock.
count clock.
Notes 1. Including case when external clock is not supplied.
2. Including case when external clock is supplied.
3.
µ
PD780344Y, 780354Y Subseries only