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CHAPTER 5 CLOCK GENERATOR
User’s Manual U15798EJ2V0UD
Figure 5-7. Examples of Incorrect Resonator Connection (2/2)
(e) Signals are fetched
Remark
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert
resistors in series on the XT2 side.
Caution When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting
in malfunction.
To prevent that from occurring, it is recommended to wire X2 and XT1 so that they are not in
parallel.
5.4.4 Divider
The divider divides the main system clock oscillator output (f
X
) and generates various clocks.
5.4.5 When no subsystem clocks are used
If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect
the XT1 and XT2 pins as follows.
XT1: Connect to V
DD0
or V
DD1
XT2: Open
In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator
when the main system clock stops. To minimize leakage current, the above internal feedback resistor can be removed
by setting bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the XT1 and XT2 pins
as described above.
IC
X2
X1
V
SS1
Содержание mPD780344 Series
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