NEC mPD780344 Series, Руководство пользователя

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CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51
User’s Manual U15798EJ2V0UD
8.6 8-Bit Timer/Event Counter 50 and 51 Cautions
(1) Timer start errors
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because 8-bit timer counter 5n (TM5n) is started asynchronously to the count pulse.
Figure 8-12. 8-Bit Timer Counter Start Timing
Count pulse
TM5n count value 00H 01H 02H 03H 04H
Timer start
Remark n = 0, 1
(2) Operation after compare register change during timer count operation
If the value after 8-bit timer compare register 5n (CR5n) is changed is smaller than the value of 8-bit timer counter
5n (TM5n), TM5n continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after
CR5n change is smaller than value (N) before the change, it is necessary to restart the timer after changing CR5n.
Figure 8-13. Timing After Compare Register Change During Timer Count Operation
Count pulse
CR5n
TM5n count value
N M
X – 1 X FFH 00H 01H 02H
Caution Except when the TI5n input is selected, always set TCE5n = 0 before setting the stop state.
Remarks 1. N > X > M
2. n = 0, 1
(3) TM5n (n = 0, 1) reading during timer operation
When reading TM5n during operation, select a count clock with a high/low level waveform longer than two cycles
of the CPU clock because the count clock stops temporarily. For example, in the case where the CPU clock
(f
CPU
) is f
X
, when the selected count clock is f
X
/4 or below, TM5n can be read.
Remark n = 0, 1