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CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U15798EJ2V0UD
(2) LCD clock control register 3 (LCDC3)
This register is used to select the LCD source clock and frame frequency.
It is set by an 8-bit memory manipulation instruction.
RESET input sets the value of this register to 00H.
Figure 18-4. Format of LCD Clock Control Register 3 (LCDC3)
Address: FF91H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
LCDC3
0
0
0
0
LCDC33
LCDC32
LCDC31
LCDC30
LCDC33
LCDC32
Source clock selection (f
LCD
)
0
0
f
XT
(32.768 kHz)
0
1
f
X
/2
6
(156.25 kHz)
1
0
f
X
/2
7
(78.125 kHz)
1
1
f
X
/2
8
(39.0625 kHz)
LCDC31
LCDC30
Selection of reference clock generating frame frequency
0
0
f
LCD
/2
6
0
1
f
LCD
/2
7
1
0
f
LCD
/2
8
1
1
f
LCD
/2
9
Caution Do not rewrite LCDC3 while the LCD is operating. Be sure to set this bit while LCDON = 0, SCOC
= 0, and VLCON = 0.
Remark
Figures in parentheses are for operation with f
X
= 10 MHz or f
XT
= 32.768 kHz
Table 18-4 shows the frame frequency if f
XT
(32.768 kHz) is used as the source clock (f
LCD
), and Figure 18-5 shows
the relationship between the reference clock that generates the frame frequency, and the frame frequency.
Table 18-4. Frame Frequency
Reference Clock Generating
f
XT
/2
9
f
XT
/2
8
f
XT
/2
7
f
XT
/2
6
Frame Frequency
Frame Frequency
Display duty
Static
64 Hz
128 Hz
256 Hz
Note
512 Hz
Note
1/3 duty
21 Hz
43 Hz
85 Hz
171 Hz
Note
1/4 duty
16 Hz
32 Hz
64 Hz
128 Hz
Note
Set so that the frame frequency is 128 Hz or lower.
Содержание mPD780344 Series
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