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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0
User’s Manual U15798EJ2V0UD
(8) Timer operation
<1>
Even if 16-bit timer counter 0 (TM0) is read, the value is not captured by 16-bit timer capture/compare
register 01 (CR01).
<2>
Regardless of the CPU’s operation mode, when the timer stops, the signals input to pins TI00/TI01 are
not acknowledged.
(9) Capture operation
<1>
If TI00 is specified as the valid edge of the count clock, the capture operation by the capture register
specified as the trigger for TI00 is not possible.
<2>
If both the rising and falling edges are selected as the valid edges of TI00, capture is not performed.
<3>
To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two of
the count clock cycles selected by prescaler mode register 0 (PRM0).
<4>
The capture operation is performed at the fall of the count clock. An interrupt request input (INTTM0n),
however, is generated at the rise of the next count clock.
(10) Compare operation
<1>
INTTM0 may not be generated if the set value of 16-bit timer capture registers 00, 01 (CR00, CR01) and
the count value of 16-bit timer counter 0 (TM0) match and CR00 and CR01 are overwritten at the timing
of INTTM0 generation. Therefore, do not overwrite CR00 and CR01 frequently even if overwriting the same
value.
<2>
Capture operation may not be performed for CR00/CR01 set in compare mode even if a capture trigger
has been input.
Содержание mPD780344 Series
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