![background image](http://html1.mh-extra.com/html/nec/mpd780344-series/mpd780344-series_user-manual_4071564192.webp)
192
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51
User’s Manual U15798EJ2V0UD
Figure 8-4. Format of Timer Clock Select Register 51 (TCL51)
Address: FF74H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
TCL51
0
0
0
0
0
TCL512
TCL511
TCL510
TCL512
TCL511
TCL510
Count clock selection
0
0
0
TI51 falling edge
0
0
1
TI51 rising edge
0
1
0
f
X
/2 (5 MHz)
0
1
1
f
X
/2
3
(1.25 MHz)
1
0
0
f
X
/2
5
(313 kHz)
1
0
1
f
X
/2
7
(78.1 kHz)
1
1
0
f
X
/2
9
(19.5 kHz)
1
1
1
f
XT
(32.768 kHz)
Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand.
2. Be sure to set bits 3 to 7 to 0.
Remarks 1.
f
X
: Main system clock oscillation frequency
2.
Figures in parentheses are for operation with f
X
= 10 MHz, f
XT
= 32.768 kHz
(2) 8-bit timer mode control register 5n (TMC5n: n = 0, 1)
TMC5n is a register which sets the following.
<1>
8-bit timer counter 5n (TM5n) count operation control
<2>
8-bit timer counter 5n (TM5n) operation mode selection
<3>
Timer output F/F (flip flop) status setting
<4>
Active level selection in timer F/F control or PWM (free-running) mode.
<5>
Timer output control
TMC5n is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the value of this register to 00H.
Figure 8-5 shows the TMC5n format.
Содержание mPD780344 Series
Страница 2: ...2 User s Manual U15798EJ2V0UD MEMO...