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CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51
User’s Manual U15798EJ2V0UD
8.3 Configuration of 8-Bit Timer/Event Counters 50 and 51
8-bit timer/event counters 50 and 51 consist of the following hardware.
Table 8-1. Configuration of 8-Bit Timer/Event Counters 50 and 51
Item
Configuration
Timer register
8-bit timer counter 5n (TM5n)
Register
8-bit timer compare register 5n (CR5n)
Timer output
2 (TO5n)
Control registers
Timer clock select register 5n (TCL5n)
8-bit timer mode control register 5n (TMC5n)
Port mode register 3 (PM3)
Note
Note
See
Figure 4-9 Block Diagram of P32 to P34
.
Remark
n = 0, 1
(1) 8-bit timer counter 5n (TM5n: n = 0, 1)
TM5n is an 8-bit read-only register which counts the count pulses.
A counter is incremented in synchronization with the rising edge of the count clock.
When the count value is read during operation, count clock input is temporary stopped, and then the count value
is read. In the following situations, the count value is set to 00H.
<1>
RESET input
<2>
When TCE5n is cleared
<3>
When TM5n and CR5n match in clear & start mode if this mode was entered upon match of the TM5n and
CR5n values.
Remark
n = 0, 1
(2) 8-bit timer compare register 5n (CR5n: n = 0, 1)
CR5n is a register that can be read/written by an 8-bit memory manipulation instruction.
The value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count value, and an interrupt
request (INTTM5n) is generated if they match, except in PWM mode.
In PWM mode, the TO5n pin becomes the active level due to TM5n overflow, and when the TM5n value and
the CR5n value match, the TO5n pin becomes the inactive level.
It is possible to rewrite the value of CR5n within 00H to FFH during a count operation.
RESET input makes the value of this register undefined.
Remark
n = 0, 1
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