![background image](http://html1.mh-extra.com/html/nec/mpd780344-series/mpd780344-series_user-manual_4071564364.webp)
364
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U15798EJ2V0UD
Figure 18-2. Format of LCD Display Mode Register 3 (LCDM3)
Address: FF90H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
LCDM3
LCDON
SCOC
VLCON
BLSEL
BLON
0
0
LCDM0
LCDON
Display control (enables output of display data)
0
Display OFF (All segment output pins output unselect signals.)
1
Display ON
SCOC
Output control of segment/common pins
0
Output GND level to segment/common pins.
1
Output select signal to segment/common pins.
VLCON
Booster circuit control
0
Stop booster circuit.
1
Operate booster circuit
BLSEL
Note 1
Blinking clock cycle selection
0
Blinking cycle of 0.5 s
1
Blinking cycle of 1.0 s
BLON
Note 2
Blinking display control
0
Blinking display OFF
1
Note 3
Blinking display ON
LCDM0
Note 4
Dynamic/static display alternate pins
Notes 5, 6
Dynamic pin
Time division
Bias mode
Time division
Bias mode
0
4
1/3
4
1/3
1
3
1/3
3
1/3
Notes 1.
The BLSEL bit is valid only when the subsystem clock is used.
2.
The corresponding segment pin can be blinked only if the blinking data memory (higher 4 bits of FA00
to FA27H) is set to 1.
3.
Do not change the contents of the blinking data memory while BLON = 1.
4.
Do not change LCDM0 while the LCD is in operation. Be sure to set this bit while LCDON = 0, SCOC
= 0, and VLCON = 0.
5.
The dynamic/static alternate pins are in the static display mode when this mode is selected by static/
dynamic display switching register 3 (SDSEL3).
6.
When static display is not used, the static display common output pin (SCOM0) outputs the GND
potential.
Содержание mPD780344 Series
Страница 2: ...2 User s Manual U15798EJ2V0UD MEMO...