MIPS MIPS32 74K Series, Руководство по программированию

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7.6 Almost Alphabetically-ordered table of DSP ASE instructions
Programming the MIPS32® 74K™ Core Family, Revision 02.14 98
extr.w rt,ac,shift Extracts a bit field from an accumulator into a general purpose register. The LS bit of the
extracted field can start anywhere from bit zero to 31 of the accumulator:
int64 ac; unsigned int rt;
rt = (ac >> shift) & 0xFFFFFFFF;
At option you can specify rounding ( _r names):
int64 ac; unsigned int rt;
rt = ((ac + 1<<(shift-1)) >> shift) & 0xFFFFFFFF;
and signed 32-bit saturation of the result (
_s
/
_rs
names).
The extrv... variants specify the shift amount (still limited to 31 positions) with a
register.
extr_r.w rt,ac,shift
extr_rs.w rt,ac,shift
extrv.w rt,ac,rs
extrv_r.w rt,ac,rs
extrv_rs.w rt,ac,rs
extr_s.h rt,ac,shift
Obtain a right-shifted value from an accumulator and form a signed 16-bit saturated
result.
extrv_s.h rt,ac,rs
insv rt,rs
The bitfield insert in the standard MIPS32 instruction set is
ins rt,rs,pos,size
,
and the position and size must be constants (encoded as immediates in the instruction
itself). This instruction permits the position and size to be calculated by the program, and
then supplied as
DSPControl[pos]
and
DSPControl[scount]
respectively.
In this case DSPControl[pos] must be set to the lowest numbered bit in the field to be
inserted: yes, that’s different from the extp... instructions.
lbux rd,index(base) Load operations with rregister address formation. lbux is a load byte and zero
extend,
lhx
loads half-word and sign-extends, and
lwx
loads a whole word. The full
address must be naturally aligned for the data type.
lhx rd,index(base)
lwx rd, index(base)
maq_s.w.phl ac,rs,rt Non-SIMD Q15 multiply-accumulate, with operands coming from either the “left”
(higher bit number) or “right” (lower bit number) half of each of the operand registers.
In all versions the Q15 multiplication is saturated to a Q31 results. The “_sa” variants
saturates the add result in the accumulator to a Q31, too.
maq_s.w.phr ac,rs,rt
maq_sa.w.phl ac,rs,rt
maq_sa.w.phr ac,rs,rt
mfhi rd, ac Legacy instruction, which now works on new accumulators (if you provide a second
nonzero argument). Copies high/low half (respectively) of accumulator to
rd .
mflo rd, ac
modsub rd,rs,rt Circular buffer index update.
rt
packs both the decrement amount (low 8 bits) and the
highest index (high 24 bits), then this instruction calculates:
rd = (rs == 0) ? ((unsigned) rt >> 8): rs - (rt & 0xFF);
mthi rs, ac Legacy instruction working on new accumulators. Moves data from
rd
to the high half of
an accumulator.
mthlip rs, ac
Moves the low half of the accumulator to the high half, then writes the GPR value in the
low half.
mtlo rs, ac Legacy instruction working on new accumulators. Moves data from
rd
to the low half of
an accumulator.
muleq_s.w.phl rd,rs,rt
Multiply selected Q15 values from “left”/“right” (higher/lower numbered bits) of rd / rs
to a Q31 result in a general purpose register, Q31-saturating.
Like all multiplies which target general purpose registers, it may well use the multiply
unit and overwrite
hi
/
lo
, also known as
ac0
.
muleq_s.w.phr rd,rs,rt
muleu_s.ph.qbl rd,rs,rt A 2
×
SIMD 16-bit
×
8-bit multiplication.
muleu_s.ph.qbl
does something like:
rd = ((LL_B(rs)*LEFT_H(rt)) << 16) |
((LR_B(rs)*RIGHT_H(rt));
Note that the multiplications are unsigned integer multiplications, and each half of the
result is unsigned-16-bit-saturated.
The asymmetric source operands are quite unusual, and note this is not a fractional com-
putation.
muleu_s.ph.qbr is the same but picks the RL and RR (low bit numbered) byte val-
ues from rs .
muleu_s.ph.qbr rd,rs,rt
mulq_rs.ph rd,rs,rt
2
×
SIMD Q15 multiplication to two Q15 results. Result in general purpose register, hi / lo
or
ac0
may be overwritten.
Table 7.2 DSP instructions in alphabetical order
Instruction Description