MIPS MIPS32 74K Series, Руководство по программированию

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3.6 Scratchpad memory/SPRAM
Programming the MIPS32® 74K™ Core Family, Revision 02.14 44
Instruction bus error exceptions are precise (when the exception happens EPC always points to the instruction where
fetch failed). But a data-side bus error is usually caused by a load, and the (non-blocking) load which caused it may
have happened a long time before the busy cycle finishes and the error is signalled. So a bus error exception caused by
a load or store is imprecise;
EPC does not necessarily (or even usually) point to the instruction causing the memory
read..
If software knows that a particular read might encounter a bus error - typically it’s some kind of probe - it should be
careful to stall and wait for the load value immediately, by reading the value into a register, and make sure it can han-
dle a bus error at that point.
There is an obscure corner case. The 74K core’s D-cache is “write-allocate”: so a write which misses in the cache will
trigger a read, to fill the cache line ready to receive the new data. If you’re unlucky enough to get a bus error on that
read-for-refill, the bus error will be associated with a store. After a bus error you can look at
ErrCtl[LBE] / ErrCtl[WABE]
to see whether the error was caused by a load or write-allocate.
3.6 Scratchpad memory/SPRAM
The 74K core (like most of MIPS Technologies’ cores) can be equipped with modestly-sized high speed on-chip data
memory, called scratchpad RAM or SPRAM. SPRAM is connected to a cache interface, alongside the I- and/or D-
cache, so is available separately for the I- and D-side (ISPRAM and DSPRAM).
MIPS Technologies provide the interface on which users can build many types and sizes of SPRAM. We also provide
a “reference design” for both ISPRAM andDSPRAM, which is what is described here. If you keep the programming
interface the same as the reference design, you’re more likely to be able to find software support. The reference
design allows for on-chip memories of up to 1Mbytes in size.
There are two possible motives for incorporating SPRAM:
• Dedicated high-speed memory: SPRAM runs with cache timing (multi-cycle SPRAM is supported for some
other MIPS Technologies cores, but not on 74K cores).
SPRAM can be made larger than the maximum cache size.
Even for smaller sizes, it is possible to envisage applications where some particularly heavily-used piece of data
is well-served by being permanently installed in SPRAM. Possible, but unusual. In most cases heavily-used data
will be handled well by the D-cache, and until you really know otherwise it’s better for the SoC designer to max-
imize cache (compatible with his/her frequency needs.)
But there’s another more compelling use for a modest-size SPRAM:
• “DMA” accessible to external masters on the OCP interface: the SPRAM can be configured to be accessible
from an OCP interface. OCP masters will see it just as a chunk of memory which can be read or written.
Because SPRAM stands in for the cache, data passed through the SPRAM in this way doesn’t require any soft-
ware cache management. This makes it spectacularly efficient as a staging area for communicating with complex
I/O devices: a great way to implement “push” style I/O (that is where the device writes incoming data close to the
CPU).
SPRAM must be located somewhere within the physical address map of the CPU, and is usually accessed through
some “cached” region of memory (uncached region accesses to scratchpad work with the 74K reference design, but
may not do so on other implementations - better to access it through cacheable regions). It’s usually better to put it in