MIPS MIPS32 74K Series, Руководство по программированию

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3.8 The TLB and translation
Programming the MIPS32® 74K™ Core Family, Revision 02.14 48
Some points to make about the TLB entry:
• The input-side virtual address fields (to the left) have the fields necessary to match an incoming address against
this entry. “VPN” is (by OS tradition) a “virtual page number” - the high bits of the program (virtual) address.
“VPN2” is used to remind you that this address is for a double-page-size virtual region which will map to a pair
of physical pages...
• The right-hand side (physical) fields are the information used to output a translation. There are a pair of outputs
for each input-match, and which of them is used is determined by the highest within-match address bit. So in
standard form (when we’re using 4Kbyte pages) each entry translates an 8Kbyte region of virtual address, but we
can map each 4Kbyte page onto any physical address (with any permission flag bits).
• The size of the input region is configurable because the “PageMask” determines how many incoming address bits
to match. The 74K core allows page sizes of 4Kbytes, 16Kbytes and going on in powers of 4 up to 256Mbytes.
That’s expressed by the legal values of
PageMask
, shown below.
• The “ASID” field extends the virtual address with an 8-bit, OS-assigned memory-space identifier so that transla-
tions for multiple different applications can co-exist in the TLB (in Linux, for example, each application has dif-
ferent code and data lying in the same virtual address region).
• The “G” (global) bit is not quite sure whether it’s on the input or output side - there’s only one, but it can be read
and written through either of
EntryLo0-1
. When set, it causes addresses to match regardless of their ASID value,
thus defining a part of the address space which will be shared by all applications. For example, Linux applica-
tions share some “kseg2” space used for kernel extensions.
3.8.2 Live translation and micro-TLBs
When you’re really tuning out the last cycle, you need to know that in the 74K core the I-side translation is done by a
little table local to the instruction fetch unit, and called the ITLB (sometimes “micro-TLB” or “uTLB”). There are
only 4 entries in the ITLB, and it is functionally invisible to software: it’s automatically refilled from the main TLB
(in this context it’s often called the joint TLB or JTLB) when required, and automatically cleared whenever the TLB is
updated. It costs six extra clocks to refill the ITLB for any access whose translation is not already present. In 74K
family cores (unlike other cores from MIPS Technologies) there is no D-side micro-TLB — D-side translation uses
the main TLB directly. uTLB entries can only map 4KB and 16KB pages (main TLB entries can handle a whole
range of sizes from 4KB to 256MB). When the uTLB is reloaded a translation marked for a size other than 4KB or
16KB is down-converted as required.
3.8.3 Reading and writing TLB entries: Index, Random and Wired
Two CP0 registers work as simple indexes into the TLB array for programming:
Index
and
Random
. The oddly-
named
Wired
controls
Random
’s behavior.
Figure 3.11 Fields in a 74K™ core TLB entry
EntryHi EntryHi
VPN2 PageMask ASID G PFN
Flags
PFN
Flags
C D V C D V
PageMask EntryLo1 EntryLo0