6.2 Basic instruction set
Programming the MIPS32® 74K™ Core Family, Revision 02.14
78
Figure 6.1 How floating point numbers are stored in a register
Just to remind you:
•
sign: FP numbers are positive numbers with a separate sign bit; “1” denotes a negative number.
•
mantissa: represents a binary number. But this is a floating point number, so the units depend on:
•
exp: the exponent.
When 32-bit data is held in a 64-bit register, the high 32 bits are don’t care.
The MIPS Architecture’s 32-bit and 64-bit floating point formats are compatible with the definitions of “single preci-
sion” and “double precision” in
FP registers can also hold simple 2s-complement signed integers too, just like the same number held in the integer
registers. That happens whenever you load integer data, or convert to an integer data type.
Floating point data in memory is endianness-dependent, in just the same way as integer data is; the higher bit-num-
bered bytes shown in
will be at the lowest memory location when the core is configured big-endian, and
the highest memory location when the core is little-endian.
6.2 Basic instruction set
Whenever it makes sense to do so, FP instructions exist in a version for each data type. In assembler that’s denoted by
a suffix of:
There’s a good readable summary of the floating point instruction set in
technical details in
As a one-minute guide: the FPU provides basic arithmetic (add, multiply, subtract, divide and square root). It’s all
register-to-register (like the integer unit). It’s written “destination first” like integer instructions; sometimes that’s
unexpected in that
cvt.d.s
is a “convert from single to double”. It has a set of multiply/add instructions which
work on four registers:
madd a,b,c,d
does
a = c*d + b
.s
single-precision
.d
double-precision
.w
32-bit integer (“word”)
.l
64-bit integer
float
double
16
23
8
15
0
7
mantissa
sign
exp
24
31
56
63
32
39
40
47
48
55
16
23
24
31
8
15
0
7
mantissa
sign
exp
Содержание MIPS32 74K Series
Страница 1: ...Document Number MD00541 Revision 02 14 March 30 2011 Programming the MIPS32 74K Core Family...
Страница 10: ...Programming the MIPS32 74K Core Family Revision 02 14 10...
Страница 20: ...1 4 A brief guide to the 74K core implementation Programming the MIPS32 74K Core Family Revision 02 14 20...
Страница 28: ...2 2 PRId register identifying your CPU type Programming the MIPS32 74K Core Family Revision 02 14 28...
Страница 54: ...3 8 The TLB and translation Programming the MIPS32 74K Core Family Revision 02 14 54...
Страница 83: ......
Страница 86: ...6 5 FPU pipeline and instruction timing Programming the MIPS32 74K Core Family Revision 02 14 86...
Страница 101: ...The MIPS32 DSP ASE 101 Programming the MIPS32 74K Core Family Revision 02 14...
Страница 134: ...8 4 Performance counters Programming the MIPS32 74K Core Family Revision 02 14 134...
Страница 154: ...C 3 FPU changes in Release 2 of the MIPS32 Architecture Programming the MIPS32 74K Core Family Revision 02 14 154...