MIPS MIPS32 74K Series, Руководство по программированию

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Memory map, caching, reads, writes and translation
37 Programming the MIPS32® 74K™ Core Family, Revision 02.14
and in C header files. I hope Table 3.1 helps. In the rest of this document we’ll either use the full software name or
(quite often) just talk of TagLo without qualification.:
3.4.6 L1 Cache instruction timing
Most CP0 instructions are used rarely, in code which is not timing-critical. But an OS which has to manage caches
around I/O operations or otherwise may have to sit in a tight loop issuing hundreds of
cache
operations at a time, so
performance can be important. Firstly, any D-side
cache
instruction will check the FSB queue (as described in
Section 3.3 “Reads, writes and synchronization” ) for potentially matching entries. The “potential match” check uses
the cache index, and avoids taking any action for most irrelevant FSB activity. But on a potential match the cacheop
waits (stalling the memory pipeline) while any pending cache refills happen, and while any dirty lines evicted from
the cache are sent out at least to the CPU’s write buffer. Typically, this will not take more than a few clocks, and will
only need to be done once for a stream of cacheops.
In the 74K core, the whole cacheop is executed in the memory pipeline, after the
cache
instruction graduates. All
cache
instructions except for “index load...” run through graduation without delay — and in particular, any stream of
hit-type operations which miss in the cache can run 1-per-clock.
A younger instruction which has run ahead of the cacheop is checked while it waits for graduation; if it might run
incorrectly because of an incomplete cacheop, the younger instruction is cancelled and the whole execution unit
backed off so it can be re-issued from scratch (an EU “replay” — expensive but infrequent).
3.4.7 L2 cache instruction timing
The L2 cache run synchronously with the CPU but at a configurable clock ratio. The L2 operations will be signifi-
cantly slower than L1 versions even at the same clock ratio. Exactly how slow is dependent on the performance of the
memory blocks used to build your L2 cache and the L2 clock ratio.
3.4.8 Cache management when writing instructions - the “synci” instruction
The
synci
instruction (new to the MIPS32 Release 2 update) provides a clean mechanism - available to user-level
code, not just at kernel privilege level - for ensuring that instructions you’ve just written are correctly presented for
Table 3.1 Caches and their CP0 cache tag/data registers
Cache CP0 Registers CP0 number
L1 I-cache
ITagLo 28.0
ITagHi 29.0
IDataLo 28.1
IDtataHi 29.1
L1 D-cache
DTagLo 28.2
DTagHi 29.2
DDataLo 28.3
L2 cache
L23TagLo
1
1. In past versions of this manual
L23TagLo
was known as
“STagLo”, and so on. But this name is more mnemonic.
28.4
L23DataLo 28.5
L23DataHi 29.5