MIPS MIPS32 74K Series, Руководство по программированию

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7.4 DSP instructions
Programming the MIPS32® 74K™ Core Family, Revision 02.14 92
7.4.6 Conversions to and from SIMD types
Conversion operations from larger to smaller fractional types have names which start “
precrq...
” for “precision
reduction, fractional”. Conversion operations from smaller to larger have names which start “
prece...
” for “preci-
sion expansion”.
• Form vector from high/low parts of two other paired-half values:
packrl.ph
makes a paired-half vector from
two half vectors, swapping the position of each sub-vector. It can be used to acquire a properly formed sub-vector
from a non-aligned data stream.
• One Q15 from a paired-half to a Q31 value:
preceq.w.phl
/
preceq.w.phr
select respectively the “left”
(high bit numbered) or “right” (low bit numbered) Q15 value from a paired-half register, and load it into the
result register as a Q31 (that is, it’s put in the high 16 bits and the low 15 bits are zeroed).
• Two bytes from a quad-byte to paired-half:
precequ.ph.qbl
/
precequ.ph.qbr
picks two bytes from
either the “left” (high bit numbered) or “right” (low bit numbered) halves of a quad-byte value, and unpacks to a
pair of Q15 fractions.
precequ.ph.qbla
does the same, except that it picks two “alternate” bytes from bits 31-24 and 15-8, while
precequ.ph.qbra
picks bytes from bits 23-16 and 7-0.
Similar instructions without the
q
-
preceu.ph.qbl
,
preceu.ph.qbr
,
preceu.ph.qbla
” and
pre-
ceu.ph.qbra
- work on the same register fields, but treat the quantities as integers, so the 16-bit results get
their low bits set.
• 2
×
Q31 to a paired-half: both operands and result are assumed to be signed fractions, so
precrq.ph.w
just
takes the high halves of the two source operands and packs them into a paired-half;
precrq_rs.ph.w
rounds
and saturates the results to Q15.
• 2
×
paired-half to quad-byte: you need two source registers to provide four paired-half values, of course. This is a
fractional operation, so it’s the low bits of the 16-bit fractions which are discarded.
precrq.qb.ph
treats the paired-half operands as unsigned fractions, retaining just the 8 high bits of each 16-
bit component.
precrqu_s.qb.ph
treats the paired-half operands as Q15 signed fractions and both rounds and saturates the
result (in particular, a negative Q15 fraction produces a zero byte, since zero is the lowest representable quantity).
• Replicate immediate or register value to paired-half: in
repl.ph
the value to be replicated is a 10-bit signed
immediate value (that’s in the range
-512
≤
x
≤
511) which is sign-extended to 16 bits, whereas in
replv.ph
the value - assumed to be already a Q15 value - is in a register.
• Replicate single value to quad-byte: there’s both a register-to-register form
replv.qb
and an immediate form
repl.qb
.
7.4.7 Multiplication - SIMD types with result in GP register
When a multiply’s destination is a general-purpose register, the operation is still done in the multiply unit, and you
should expect it to overwrite the
hi / lo registers (otherwise known as ac0 .)
• 8-bit
×
16-bit 2-way SIMD multiplication:
muleu_s.ph.qbl
/
muleu_s.ph.qbr
picks the “left” (high bit
numbered) or “right” (low bit numbered) pair of byte values from one source register and a pair of 16-bit values