MIPS MIPS32 74K Series, Руководство по программированию

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3.7 Common Device Memory Map
Programming the MIPS32® 74K™ Core Family, Revision 02.14 46
Don’t forget to set ErrCtl[SPR] back to zero when you’re done.
3.7 Common Device Memory Map
In order to preserve the limited CP0 register address space, many new architectural enhancements, particularly those
requiring several registers, will be memory mapped, that is, accessed by uncached load and store instructions. In order
to avoid creating dozens of memory regions to be managed, the common device memory map (CDMM) was created
to group them into one region. A single physical address region, up to 32KB, is defined for CDMM. The address of
this region is programmable via the
CDMMBase CP0 register shown in Figure 3-9 .
Having this region physically addressed enables some additional access controls. On a core with a TLB, the region
would typically be located in the first 256MB, allowing direct kseg1 access. However, if user or supervisor access was
desired, TLB mappings could be established to map a useg address to the same region. On FMT based cores, it might
be mapped to a kseg1 address if user access was not needed, or to a useg/kuseg address if it was.
The block of addresses is further broken up into 64-byte Device Register Blocks(DRB). A ‘device’ (feature requiring
memory mapped accesses), can use from 1-63 DRBs - up to 4KB of addressable registers. The first 64 bits of the first
DRB associated with a device is allocated for an Access Control and Status Register (of which only 32 are in use cur-
rently). The ACSR provides information about the device - ID, version, and size - and also contains control bits that
can enable user and supervisor read and/or write access to the device. This register is shown in
Figure 3.10
CDMM devices are packed into the lowest available DRBs. Starting with 0 (or 1 if CDMMBase[CI] ==1), software
should read the ACSR, determining both the current device type as well as the starting location for the next device.
Iterating through this process will create a map of all devices which you would presumably store in a more convienent
format.
The first device that has been defined in CDMM is the Fast Debug Channel which is described in Section
8.1.10 “Fast Debug Channel” . This device is a UART-like communication channel that utilizes the EJTAG pins for
off-chip access. The UART is a natural fit for a memory mapped device, although many types of devices can be envi-
sioned.
Figure 3-9 Fields in the CDMMBase Register
Where:
CDMM_UPPER_ADDR:
: This field contains the upper bits of the base physical address of the CDMM region. This field
is shifted by 4b, so that bits 31..11 correspond to PA bits 35..15. Unimplemented physical address bits such as 35..32
in many cores will be tied to 0.
EN
: Enables CDMM. When this bit is cleared, loads and stores to the CDMM region will go to memory. This bit resets
to 0 to avoid stepping on other things in the system address map.
CI:
Indicates that the first 64-byte device register block is reserved for additional CDMM information and is not a nor-
mal device. This extra information hasn’t been dreamed up yet, so this field should just be treated as reserved.
CDMMSize:
This field indicates how many 64-byte device register blocks are in the CDMM region. (0 means 1 DRB
and so forth)
31 11 10 9 8 0
CDMM_UPPER_ADDR EN CI CDMMSize
0