MIPS MIPS32 74K Series, Руководство по программированию

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Memory map, caching, reads, writes and translation
31 Programming the MIPS32® 74K™ Core Family, Revision 02.14
The WBB (Write Back Buffer) queue holds data waiting to be sent out over the system interface, either from D-cache
writebacks or uncached/write-through store instructions.
FSB (Fill Store buffer) queue entries are used to hold data that is waiting to be written into the D-cache. An FSB entry
gets used during a cache miss (when it holds the refill data), or a write which hits in the cache (when it holds the data
the CPU wrote). Loads and stores snoop the FSB so that accesses to lines “in flight” can be dealt with correctly.
All this has a number of consequences which may be visible to software:
• Number of non-blocking loads which may be pending: the CPU has nine LDQ entries. That limits the number of
outstanding loads.
• Hit-under-miss: the D-cache continues to supply data on a hit, even when there are outstanding misses with data
in flight. FSB entries remember the in-flight data. So it is quite normal for a read which hits in the cache to be
“completed” - in the sense that the data reaches a register - before a previous read which missed.
• Write-under-miss: the CPU pipeline continues and can generate external store cycles even though a read is pend-
ing, so long as WBB slots are available. The 74K core’s “OCP” interface is non-blocking too (reads consist of
separate address and data phases, and writes are permitted between them), so this behavior can often be visible to
the system.
• Miss under miss: the 74K core can continue to run until the pending read operations exhaust FSB or LDQ entries.
More often, of course, it will try to use the data from the pending miss and stall before it gets that far.
• Core interface ordering: at the core interface, read operations may be split into an address phase and a later data
phase, with other bus operations in between.
The 74K core - as is permitted by [MIPS32] - makes only limited promises about the order in which reads and
writes happen at the system interface. In particular, uncached or write-through writes may be overtaken by cache
line reads triggered by a load/store cache miss later in sequence. However, uncached reads and writes are always
presented in their program sequence. When some particular program needs to do things “really in order”, the
sync
instruction can help, as described in the next section.
Cache management operations interact with several queues: see Section 3.4.6 “L1 Cache instruction timing” .
3.3.2 The “sync” instruction in 74K
™
family cores
If you want to be sure that some other agent in the system sees a pair of transactions to uncached memory in the order
of the instructions that caused them, you should put a
sync
instruction between the instructions. Other MIPS32/64-
compliant CPUs may reorder loads and stores even more; portable code should use
sync
7
.
But sometimes it’s useful to know more precisely what
sync
does on a particular core. On 74K
sync
:
• Stalls graduation (preventing any later load/store from graduating and becoming externally visible) until all
pending reads, cached writes and OCP writes are completed — that is, until the FSB and WBB are empty;
• In some systems the CPU will also generate a synchronizing transaction on the OCP system interface if
Config7[ES] bit is set
8
. Not all systems do this. See Section B.2.1 “The Config7 register” for more details.
7. Note that
sync
is described as only working on “uncached pages or cacheable pages marked as coherent”. But
sync
also
acts as a synchronization barrier to the effects produced by routine cache-manipulation instructions - hit-writeback and hit-
invalidate.