MIPS MIPS32 74K Series, Руководство по программированию

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3.4 Caches
Programming the MIPS32® 74K™ Core Family, Revision 02.14 32
A new set of lightweight SYNC instructions have been introduced. As compared to the completion barrier, the order-
ing barrier is a lighter-weight operation as it does not require the specified instructions before the SYNC to be already
completed. Instead it only requires that those specified instructions which are subsequent to the SYNC in the instruc-
tion stream are never re-ordered for processing ahead of the specified instructions which are before the SYNC in the
instruction stream. This potentially reduces how many cycles the barrier instruction must stall before it completes.
Because the core processes loads and stores in order, ordering barriers are much lighter weight. Details about the set
of supported lightweight SYNC instructions can be found in the Software User’s Reference Manual
3.3.3 Write gathering and “write buffer flushing” in 74K
™
family cores
We mentioned above that writes to the system (whether uncached writes or cache write-backs) are performed some-
what lazily, the write being held in the WBB queue until a convenient moment. That can have two system-visible
effects:
• Writes can happen later than you think. Your write will happen before the next uncached read or write, but that’s
all you know. And your write might still be posted somewhere in a system controller, unless you know your sys-
tem is built to prevent it. Sometimes it’s better to code a dummy uncached read from a nearby location (which
will “flush out” buffered writes on pretty much any system).
• If your cache is configured for write-through, then cached writes to locations in the same “cache line”-sized
chunk of memory may be gathered - stored together in the WBB, and then dealt with by a single “wider” OCP
write than the one you originally coded. Sometimes, this is what you want. When it isn’t, put a
sync
between
your successive writes. Regular uncached writes are never merged, but special “uncached accelerated” writes
may be — see Section
3.4.3 below.
3.4 Caches
Most of the time caches just work and are invisible to software... though your programs would go twenty times slower
without them. But this section is about when caches aren’t invisible any more.
Like most modern MIPS CPUs, the 74K core has separate primary I- and D-caches. They are virtually-indexed and
physically-tagged, so you may need to deal with cache aliases, see
Section 3.4.9, "Cache aliases" . The design pro-
vides for 16Kbyte, 32Kbyte or 64Kbyte caches; but the largest of those are likely to come with some speed penalty.
The 74K core’s primary caches are 4-way set associative.
Your 74K core can optionally be built with a L2 (level 2 or secondary) cache. see section below for details.
But don’t hard-wire any of this information into your software. Instead, probe the Config1 register defined by
[MIPS32] (and described in ) to determine the shape and size of the L1 and any L2 cache.
3.4.1 The L2 cache option
The L2 cache is an option available to your SoC builder. Basic facts and figures:
• The L2 cache is attached to the core’s standard 64-bit OCP system interface, and when you fit it everything else
is attached to the core through the L2 cache, which has a system-side interface for that purpose. The core-side
8. This will be a read with the signal OC_MReqInfo[3] set. Handling of this transaction is system dependent, but a typical sys-
tem controller will flush any external write buffers and complete all pending transactions before telling the CPU that the
transaction is completed. Ask your system integrator how it works in your SoC.