MIPS MIPS32 74K Series, Руководство по программированию

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Memory map, caching, reads, writes and translation
43 Programming the MIPS32® 74K™ Core Family, Revision 02.14
Figure 3.7 Fields in the ErrCtl Register
Two fields are ‘overflow’ from the CacheErr register and relate to the error state:
FE/SE
: Used to detect nested errors. FE (FirstError) is set on any cache error. SE (Second Error) is set when an error is
seen and FE is set. Software should clear FE once it has logged enough error information that taking a second error
will not be fatal.
The rest of the fields can be summarized as such: running software should set just the parity enable (
PE
) bit to enable
cache parity checking as required, and leave it zero otherwise. The fields are as follows:
PE
: 1 to enable cache parity checking. Hard-wired to zero if parity isn’t implemented.
PO
: (parity overwrite) - set 1 to set the parity bit regardless of parity computation, which is only for diagnostic/test pur-
poses.
After setting this bit you can use
cache IndexStoreTag
to set the cache data parity to the value currently in
ErrCtl[PI]
(for I-cache) or
ErrCtl[PD]
(for D-cache), while the tag parity is forcefully set from
TagLo[P]
.
WST
: test mode for
cache IndexLoadTag
/
cache IndexStoreTag
instructions, which then read/write the
cache’s internal "way-selection RAM" instead of the cache tags.
SPR
: when set, index-type
cache
instructions work on the scratchpad/SPRAM, if fitted - see Section 3.6, "Scratchpad
memory/SPRAM" .
PI/PD
: parity bits being read/written to caches (I- and D-cache respectively).
LBE, WABE
: field indicating whether a bus error (the last one, if there’s been more than one) was triggered by a load or
a write-allocate respectively: see below. Where both a load and write-allocate are waiting on the same cache-line
refill, both could be set. These bits are “sticky”, remaining set until explicitly written zero.
L2P
: Controls ECC checking of an L2 cache, if it's fitted and has that capability.
For backward-compatibility, you only set
L2P
when you want to make a different error-checking choice at the L1 and
L2 levels. So L2 error checking is enabled if
ErrCtl[PE,L2P]
== 01 or
ErrCtl[PE,L2P]
== 10.
PCD
: when set 1,
cache StoreData
does not update I-cache precode bits, nor their parity. This is for deep diagnostic
only.
DYT
: set 1 to arrange that
cache
load/store data operations work on the “dirty array” — the slice of cache memory
which holds the “dirty” bits.
3.5 Bus error exception
The CPU’s “OCP” hardware interface rules permit a slave device attached to the system interface to signal back when
something has gone wrong with a read. This should not be used to report a read parity error; if parity is checked exter-
nally, it would have to be reported through an interrupt. Typically a bus error means that some subsystem has failed to
respond. Bus errors are not signalled on an OCP write cycle, and (if they were) the 74K core ignores them.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 12 11 4 3 0
PE PO WST SPR PCO ITC LBE WABE L2P PCD DYT SE FE 0 PI PD
0 0 0 0 0 0 0 0 0 0