MIPS MIPS32 74K Series, Руководство по программированию

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The MIPS32® DSP ASE
99 Programming the MIPS32® 74K™ Core Family, Revision 02.14
mulsaq_s.w.ph ac,rs,rt ac += (LEFT_H(rs)*LEFT_H(rt)) -
(RIGHT_H(rs)*RIGHT_H(rt));
The multiplications are done to Q31 values, saturated if they overflow (which is only
possible when
-1¥
-1 makes
+1
). The accumulator is really a Q32.31 value, so is
unlikely to overflow; no overflow check is done on the accumulation.
packrl.ph rd,rs,rt pack a “right” and “left” half from different registers, ie
rd = (((rs & 0xFFFF) << 16) | (rt >> 16) & 0xFFFF);
pick.ph rd,rs,rt
Like a 2-way SIMD conditional move:
ph rd,rs,rt;
rd.l = DSPControl[ccond1] ? rs.l: rt.l;
rd.r = DSPControl[ccond0] ? rs.r: rt.r;
pick.qb rd,rs,rt
Kind of a 4-way SIMD conditional move:
qb rd,rs,rt;
rd.ll = DSPControl[ccond3] ? rs.ll: rt.ll;
rd.lr = DSPControl[ccond2] ? rs.lr: rt.lr;
rd.rl = DSPControl[ccond1] ? rs.rl: rt.rl;
rd.rr = DSPControl[ccond0] ? rs.rr: rt.rr;
preceq.w.phl rd,rt
Convert a Q15 value (either left/high or right/low half of rt ) to a Q31 value in rd .
preceq.w.phr rd,rt
precequ.ph.qbl rd,rt
Simultaneously convert two unsigned 8-bit fractions from rt to Q15 and load into the two
halves of
rd
.
precequ.ph.qbl
uses rt.ll / rt.lr ;
precequ.ph.qbla
uses rt.ll / rt.rl ;
pre-
cequ.ph.qbr uses
rt.rl
/
rt.rr
; and precequ.ph.qbra uses
rt.lr
/
rt.rr
.
precequ.ph.qbla rd,rt
precequ.ph.qbr rd,rt
precequ.ph.qbra rd,rt
preceu.ph.qbl rd,rt
Zero-extend two unsigned byte values from rt to unsigned 16-bit and load into the two
halves of
rd
.
preceu.ph.qbl
uses rt.ll / rt.lr ;
preceu.ph.qbla
uses rt.ll / rt.rl ;
pre-
ceu.ph.qbr uses
rt.rl
/
rt.rr
; and preceu.ph.qbra uses
rt.lr
/
rt.rr
.
preceu.ph.qbla rd,rt
preceu.ph.qbr rd,rt
preceu.ph.qbra rd,rt
precrq.ph.w rd,rs,rt precrq.ph.w
makes a paired-Q15 value by taking the MS bits of the Q31 values in rs
and
rt
, like this:
rd = (rs & 0xFFFF0000) | ((rt>>16) & 0xFFFF);
precrq_rs.ph.w is the same, but rounds and Q15-saturates both half-results.
precrq_rs.ph.w rd,rs,rt
precrq.qb.ph rd,rs,rt Form a quad-byte value from two paired-halves. We use the upper 8 bits of each half-
word value, as if we were converting an unsigned 16-bit fraction to an unsigned 8-bit
fraction. In C:
rd = (rs & 0xFF000000) | (rs<<8 & 0xFF0000) |
(rt>>16 & 0xFF00) | (rt>>8 & 0xFF);
precrqu_s.qb.ph
Does the same, but each conversion is rounded and saturated to an unsigned byte. Note
in particular that a negative Q15 quantity yields a zero byte, since zero is the smallest
representable value.
precrqu_s.qb.ph rd,rs,rt
raddu.w.qb rd,rs
Set rd to the unsigned 32-bit integer sum of the four unsigned bytes in rs .
rddsp rt,mask
Read the contents of the DSPControl register into rt , but zeroing out any fields for
which the appropriate mask bit is zeroed, see Figure 7.1 above.
repl.ph rd,imm Replicate the same signed value into the two halves of a PH value in
rd
; the value is
either provided as an immediate whose range is limited between -512 and +511
(
repl.ph ) or from the
rt
register ( replv.ph ).
replv.ph rd,rt
repl.qb rd,imm Replicate the same 8-bit value into all four parts of a QB value in
rd
; the value can come
from an immediate constant, or the rt register of the
replv.qb
instruction.
replv.qb rd,rt
shilo ac,shift Do a right or left shift (use a negative value for a left shift) of a 64-bit accumulator. The
right shift is “logical”, bringing in zeroes into the high bits.
shilo takes a constant shift amount, while shilov get the shift amount from
rs
. The
shift amount may be no more than 31 right or 32 left.
shilov ac,rs
Table 7.2 DSP instructions in alphabetical order
Instruction Description