MIPS MIPS32 74K Series, Руководство по программированию

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C.2 User-level changes with Release 2 of the MIPS32® Architecture
Programming the MIPS32® 74K™ Core Family, Revision 02.14 152
C.2.2 Release 2 of the MIPS32® Architecture - Hardware registers from user mode
The hardware registers provide useful information about the hardware, even to unprivileged (user-mode) software,
and are readable with the
rdhwr
instruction. [MIPS32] defines four registers so far. The OS can control access to
each register individually, through a bitmask in the CP0 register HWREna - (set bit 0 to enable register 0 etc).
HWREna is cleared to all-zeroes on reset, so software has to explicitly enable user access. Privileged code can access
any hardware register.
The five registers are:
• CPUNum (0): Number of the CPU on which the program is currently running. This comes directly from the
coprocessor 0
EBase[CPUNum] field.
• SYNCI_Step (1): the effective size of an L1 cache line
32
; this is now important to user programs because they can
now do things to the caches using the
synci
instruction to make instructions you’ve written visible for execu-
tion. Then SYNCI_Step tells you the “step size” - the address increment between successive
synci
’s required
to cover all the instructions in a range.
If
SYNCI_Step returns zero, that means that you don’t need to use
synci
at all.
Table C.2 Release 2 of the MIPS32® Architecture - new instructions
Instruction(s) Description
ehb
jalr.hb rd, rs
jr.hb rs
Hazard barriers; wait until side-effects from earlier instructions are all complete (that is,
can be guaranteed to apply in full to all instructions issued after the barrier).
These defend you respectively against:
ehb - execution hazards (side-effects of old instructions which affect how an instruction
executes, but excluding those which affect the instruction fetch process).
jalr.hb / jr.hb - hazards of all kinds.
Note that
eret
is also a barrier to all kinds of hazard.
ext rt, rs, pos, size
ins rt, rs, pos, size
Bitfield extract and insert operations.
mfhc1 rt, fs
mthc1 rt, fs
Coprocessor/general register move instructions targeting the high-order bits of a 64-bit
floating point unit (CP1) register when the integer core is 32-bit.
mfhc2 rt, rd
mthc2 rt, rd
Coprocessor2 might be 64 bits, too (but this is typically a customer special unit).
rdhwr rt,rd “read hardware register” - user-mode access read-only access to low-level CPU informa-
tion - see “Hardware Registers” below.
rotr rd, rt, sa
rotrv rd, rt, rs
Bitwise rotate instructions (like shifts, one has the rotate amount as an immediate field
sa , the other in an additional register argument rs ).
seb rd, rt
seh rd, rt
Register-to-register sign extend instructions.
synci offset(base)
Synchronize caches to make instruction write effective. Instructions written by the CPU
for itself to execute must be written back from the D-cache and any stale data at that loca-
tion invalidated from the I-cache, before it will work properly.
synci
is a user-privilege
instruction which does all that is required for the enclosing cache-line sized memory
block. Very useful to JIT interpreters.
wsbh rd, rt
swap the bytes in each halfword within a 32-bit word. It was introduced together with the
rotate instructions
rot / rotv and the sign-extenders seb / seh .
Between them you can make big savings on common byte-twiddling operations; for
example, you can swap the bytes in
$2 using rot $2, $2, 16; wsbh $2, $2 .
32. Strictly, it’s the lesser of the I-cache and D-cache line size, but it’s most unusual to make them different.