MIPS MIPS32 74K Series, Руководство по программированию

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B.3 Registers for Cache Diagnostics
Programming the MIPS32® 74K™ Core Family, Revision 02.14 148
When it is set to “1”, the
sync
instruction will be signalled on the core’s OCP interface as an “ordering barrier” trans-
action, using a
sync
-specific encoding.
Config7[ES]
bit cannot be set (will always read zero and will have no effect) unless the OCP input signal
SI_SyncTxEn
is asserted — it’s interpreted as agreement from the connected OCP device/interconnect that it can
handle the barrier transaction.
The remaining fields default to zero and are uncommonly set. It is therefore always safe not to write
Config7
. Some
of these bits are for diagnostics and experimentation only:
Config7[ULB]
: set 1 to make all uncached loads blocking (a program usually only blocks when it uses the data which is
loaded). You want to do this only when nothing else will work...
Config7[BP]
: when set, no branch prediction is done, and all branches and jump stall as above.
Config7[RPS]
: when set, the return address branch predictor is disabled, so
jr $31
is treated just like any other jump
register. Instruction fetch stalls after the branch delay slot, until the jump instruction reaches the "EX" stage in the
pipeline and can provide the right address (typically adds 5 clocks compared to a successfully predicted return
address).
Config7[BHT]
: when set, the branch history table is disabled and all branches are predicted taken. This bit is don’t care
if
Config7[BP]
is set.
Config7[SL]
: when set, disables non-blocking loads. Normally the 74K core will keep running after a load instruction
even if it misses in the D-cache, until the data is used. With this disable bit set, the CPU will stall on any load D-
cache miss.
B.3 Registers for Cache Diagnostics
Registers for regular OS-used operations on the cache and scratchpad are described in Chapter 3, “Memory map,
caching, reads, writes and translation” on page 29 . But there are quite a few extra CP0 registers (or different views of
familiar registers) which are solely for the use of test/diagnostic software, and they are described here.
B.3.1 Different views of ITagLo/DTagLo
The 74K core’s cache memory is organized with separate RAMs to hold both “way select” information (which must
be updated to provide information for LRU replacement of cache lines) and “dirty bits” (only for the D-cache,
updated on any write). By keeping this information in separate RAMs, we don’t need to write the main cache tag
memory on a read or write which hits in the cache. But that memory is there, so thorough diagnostics should be able
to test it. You access these memories by setting bits in the
ErrCtl
register and then doing index-load-tag and index-
store-tag cacheops on the appropriate cache, which stage data through the ITagLo/DTagLo registers. For each mem-
ory the fields of the registers change.
The way-select RAM is an independent slice of the cache memory (distinct from the tag and data arrays). Test soft-
ware ca access either by
cache
load-tag/store-tag operations when ErrCtl[WST] is set: then you get the data in these
fields.
Figure B.3 Fields in the TagLo-WST Register
31 24 23 20 19 16 15 10 9 8 7 6 1 0
U LP L LRU 0 U 0 U