4.12 Multiply/divide unit and timings
Programming the MIPS32® 74K™ Core Family, Revision 02.14
66
No multiply/divide operation ever produces an exception - even divide-by-zero is silent — compilers typically insert
explicit check code where it’s required.
Timing varies. Multiply-accumulate instructions (there are many different flavors of MAC in the DSP ASE) have
been pipelined and tuned to achieve a 1-instruction-per-clock repeat rate, even for sequences of instructions targeting
the same accumulator. But because that requires a relatively long pipeline, multiply/divide unit instructions which
produce a result in a GP register are relatively “slow”: for example, an instruction consuming the register value from
a
mflo
will not be issued until at least 7 cycles after the
mflo
.
Divides are much slower again. All the timings are summarized in
What that means is that in an instruction sequence like:
mult $1, $2
mflo $3
addu $2, $3, 1
The
mflo
will be issued 4 cycles after the
mult
, and the
addu
will go at least 2 cycles after the
mflo
. The execution
unit may (or may not) be able to find other instructions to keep it busy, but each trip through that code sequence will
take a minimum of 9 cycles.
Содержание MIPS32 74K Series
Страница 1: ...Document Number MD00541 Revision 02 14 March 30 2011 Programming the MIPS32 74K Core Family...
Страница 10: ...Programming the MIPS32 74K Core Family Revision 02 14 10...
Страница 20: ...1 4 A brief guide to the 74K core implementation Programming the MIPS32 74K Core Family Revision 02 14 20...
Страница 28: ...2 2 PRId register identifying your CPU type Programming the MIPS32 74K Core Family Revision 02 14 28...
Страница 54: ...3 8 The TLB and translation Programming the MIPS32 74K Core Family Revision 02 14 54...
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Страница 86: ...6 5 FPU pipeline and instruction timing Programming the MIPS32 74K Core Family Revision 02 14 86...
Страница 101: ...The MIPS32 DSP ASE 101 Programming the MIPS32 74K Core Family Revision 02 14...
Страница 134: ...8 4 Performance counters Programming the MIPS32 74K Core Family Revision 02 14 134...
Страница 154: ...C 3 FPU changes in Release 2 of the MIPS32 Architecture Programming the MIPS32 74K Core Family Revision 02 14 154...