MIPS MIPS32 74K Series, Руководство по программированию

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Memory map, caching, reads, writes and translation
33 Programming the MIPS32® 74K™ Core Family, Revision 02.14
interface is enhanced and augmented to support
cache
instructions targeted at the L2, and to carry back perfor-
mance counter information and so on.
• The L2 ‘s size can be 128Kbytes, 256Kbytes, 512Kbytes or 1Mbyte. However, there are options which allow the
SoC builder to have one or more of the ways of the cache memory array visible as normal system memory
instead. There’s very little in this manual about that option. — see
“MIPS® PDtrace™ Interface and Trace
Control Block Specification”, MIPS Technologies document MD00439. Current revision is 4.30: you need
revision 4 or greater to get multithreading trace information. [L2CACHE]
.
• The L2 cache is indexed and tagged with the physical address, so is unaffected by cache aliases.
• Cache lines are either 32 bytes long (matching the L1 caches) or 64 bytes. The L2 cache’s memories are accessed
256 bits at a time internally, though it has 64-bit interfaces.
• It can be configured with 4-way or 8-way set-associative organization. In a 4-way cache the line replacement pol-
icy is “least recently used” (LRU); true LRU is impractical for an 8-way set associative cache, so something sim-
pler (a “pseudo-LRU”) is used.
• The cache has an option for error detection and correction. 1-bit data errors can be corrected and all 2-bit errors
detected with an 8-bit-per-doubleword ECC field. Check bits are provided on cache tags, too. If your L2 has ECC
fitted,
ErrCtl[L2P] will be writable — see Section 3.4.17 “ErrCtl register” for details.
• The cache is write-back but does not allocate a line on a write miss (write miss data is just sent directly to the sys-
tem memory). It is write-through for memory regions which request that policy -- see
Section
3.4.2 “Cacheability options” for details.
• The L2 cache can run synchronously to the CPU core, but (particularly for memory arrays larger than
256Kbytes) would typically then be the critical path for timing. It will more often use a 1:2 or 2:3 clock ratio.
The L2’s far-side OCP interface may run at any of a wide range of ratios from the L2 clock down.
• In an effort to keep everything going the cache manages multiple outstanding transactions (it can handle as many
as 15 outstanding misses). Misses are resolved and responses sent as they happen, not in the order of presenta-
tion.
• Latency: the L2 logic allows the memory access to be pipelined, a reasonable choice for larger or slower arrays:
ask your SoC builder. The L2 delivers hit data in a burst of four 64-bit doublewords. The first doubleword
appears after 9 or 10 L2 clocks (10 for pipelined-array systems) and the rest of the burst follows on consecutive
clocks. Added to this is some extra time taken for the original L1 miss to be discovered, synchronizing to the L2
clock, and returning the data to the CPU: typically, add 5 CPU clocks.
An L2 miss is slightly more expensive than an L1 miss from the same memory, since we don’t start the memory
access until we’ve discovered that the data isn’t in the L2. The L2 memory interface can be configured to be 64-
bit or 256-bit wide. An L2 miss will deliver miss data to the CPU core in burst of four 64-bit doublewords
.Because the CPU connects to the rest of the system through the L2 cache, it also adds 4 L2 cycles to the latency
of all transactions which bypass the L2.
• The L2 cache requires software management, and you can apply the same
cache
instructions to it as to the L1 D-
cache.
3.4.2 Cacheability options
Any read or write made by the 74K core will be cacheable or not according to the virtual memory map. For addresses
translated by the TLB the cacheability is determined by the TLB entry; the key field appears as
EntryLo[C] . Table 3.3