MIPS MIPS32 74K Series, Руководство по программированию

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B.2 Registers for CPU Configuration
Programming the MIPS32® 74K™ Core Family, Revision 02.14 146
Table B.6 Fields in the Config7 Register
Config7[WII] : Read-only bit which tells you how
wait
behaves. When this bit is set, an interrupt which would occur
just so long as Status[IE] is set 1 will always be enough to terminate a
wait
instruction.
74K family CPUs where WII reads 0 will remain in the wait condition forever if entered with interrupts disabled.
The MIPS32 Architecture Specification permits either behavior.
But with the WII -set feature it’s safe to
wait
with interrupts disabled using Status[IE] or TCStatus[IXMT] . This
allows OS code to avoid a tricky race condition.
Config7[FPFS] : enable bit for the
pref 31
prefetch, which is fast but can create a security leak, as described in Table
4.1 . When this bit isn’t set,
pref 31
will behave exactly like
pref 30
.
Config7[IHB]: When set, this bit will remove the need for most hazard barrier instructions (see Section 5.1 “Hazard
barrier instructions” ) by doing two things. Firstly, it will automatically prevent the hazard which could arise because
one instruction produces a CP0 register value and a later instruction (which is one of
mfc0
,
di
,
ei
,
eret
or
deret
)
consumes that value. Secondly, any
jalr
or
jr
instruction run in kernel mode will act as an execution hazard barrier
(in fact, just like the corresponding
jalr.hb
or
jr.hb
). IHB is clear by default, which is fine so long as your code
inserts all the hazard barrier instructions required by [MIPS32] .
Config7[SEHB] : "Slow EHB": mode to fix CP0 sequences relying on strong semantics of
ehb
found on older CPUs.
By default,
ehb
will check whether any instructions in flight are directly writing CP0 registers: if such instructions
exist, it will block issue of instructions from the instruction buffer until all older instructions have graduated and the
pipe is empty. This eliminates CP0 dependencies, leading to an 11-clock bubble only when necessary. If your soft-
ware is using ehb according to the recommendations of
[MIPS32] that will be fine.
In other CPUs the effect of
ehb
may be unconditional, and some sequences might have relied on that. Set this bit to
make
ehb
block unconditionally, regardless of what instructions are in flight.
Config7[CP1IO,CP2IO] : By default data sent from the core to a coprocessor block is sent in an order reflecting the
internal pipeline execution sequence. Set either of these bits to arrange that for CP1/CP2 respectively, data will be
sent only in instruction order.
Data from the core to the CP is tagged with an “age” field. MIPS Technologies' standard FPU accepts data out-of-
order, interpreting the age field to associated data with the correct instruction. So
CP1IO should not be set for the
standard FPU, unless you can think of some debug use.
Config7[IALU,IAGN] : Selective control of out-of-order behavior: issue ALU-side or load/store-side instructions
(respectively) in program order.
Config7[DGHR] : Make BHT fall back to simple bi-modal predictor (by default it uses a superior "GShare" algorithm).
Config7[SG] : Set 1 to allow only one instruction to graduate per cycle: not good for performance, probably only for
test purposes.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WII FPFS IHB FPR1 SEHB CP2IO IAGN IALU
DGH
R
SG SUI 0 HCI FPR0 AR 0 PREF IAR IVA ES 0 CP1IO 0 ULB BP RPS BHT SL