MIPS MIPS32 74K Series, Руководство по программированию

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Memory map, caching, reads, writes and translation
39 Programming the MIPS32® 74K™ Core Family, Revision 02.14
available but your software doesn’t need it, you can restore “legacy” behavior by setting Config7[IVA] to 1. Refer to
Section B.2.1 “The Config7 register” for details.
The MIPS Technology supplied L2 cache (if configured) is physically indexed and physically tagged, so does not suf-
fer from aliases.
3.4.10 Cache locking
[MIPS32] provides for a mechanism to lock a cache line so it can’t be replaced. This avoids cache misses on one par-
ticular piece of data, at the cost of reducing overall cache efficiency.
Caution: in complex software systems it is hard to be sure that cache locking provides any overall benefit - most often,
it won’t. You should probably only use locking after careful measurements have shown it to be effective for your
application.
Lock a line using a
cache FetchAndLock
(it will not in fact re-fetch a line which is already in the cache). Unlock
it using any kind of relevant
cache
“invalidate” instruction
10
- but note that
synci
won’t do the job, and should not
be used on data/instruction locations which are cache-locked.
3.4.11 Cache initialization and tag/data registers
The cache tag and data registers — listed in Table 3.1 above — are used for staging tag information being read from
or written to the cache. [MIPS32] declares that the contents of these registers is implementation dependent, so they
need some words here.
The “I-” registers are used for the I-cache and the “D-” registers for the D-cache
11
. Some other MIPS CPUs use the
same staging register(s) for all caches, and even simple initialization software written for such CPUs is not portable to
the 74K core.
Before getting into the details, note that it’s a strong convention that you can write all-zeros to both TagLo registers
and then use
cache IndexStoreTag
to initialize a cache entry to a legitimate (but empty) state. Your cache ini-
tialization software should rely on that, not on the details of the registers.
Only diagnostic and test software will need to know details; but Figure 3.2 shows all the fields (there’s no “D”-for-
dirty bit in 74K cores, where access to the dirty bits is done separately, see Section B.3.1 “Different views of ITagLo/
DTagLo” :
Figure 3.2 Fields in the TagLo Registers
The cache tag registers
ITagLo
and
DTagLo
can be used in special modes, controlled by bits in the
ErrCtl
register,
where the register layout changes completely. Set
ErrCtl[SPR]
for access to SPRAM control fields, as described in
Figure 3.8 and its notes below. Set
ErrCtl[WST]
or
ErrCtl[DYT]
for diagnostic-only access to the “way select” or “dirty
bit” sections of the cache control memory, as described in Section B.3.1 “Different views of ITagLo/DTagLo” . But
let’s look at the standard fields first:
10. It’s possible to lock and unlock lines by manipulating values in the
TagLo
register and then using a
cache Index_Load_Tag
instruction... but highly non-portable and likely to cause trouble. Probably for diagnostics only.
11. Some documentation just numbers the TagLo registers, starting from 0 and in the same order as their CP0 numbering: see
Table 3.1 in this chapter.
31 12 11 10 9 8 7 6 5 4 2 1 0
PTagLo U 0 V E L 0 P1 P0