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8-54
KHA1000
IEEE 488.2 status event command
Refer to Section 8.6 “ SCPI and IEEE-488.2 Common Commands .”
Event status register
The event status register sets the bit for a specific event caused by operation of this
product. Every bit of the event status register is set by the error event queue.
The register is defined by the IEEE 488.2 standard and controlled by IEEE 488.2
common commands *ESE, *ESE?, and *ESR?.
Table 8-7 Event status register
(Standard Event Status Resister)
Bit
Bit
weight
Bit name Description
0 1
Operation Complete
(OPC)
This bit is set when every standby operation
is completed after the *OPC command is
received.
The Event 800 Operation complete message
is loaded to the error/event queue.
1 2 Request Control (RQC) Not used
2 4 Query Error (QYE)
This bit is set when an attempt is made to
read data from the output queue even though
there is no output data or the system is not in
the wait state. The bit indicates that there is
no data remains in the output queue.
3 8
Device Dependent Error
(DDE) This bit is set when a device-specific error
exists.
4 16 Execution Error (EXE)
This bit is set when this product recognizes
that the program data following the header is
out of the formal input range or is not
compatible with the performance of this
product. It indicates that an effective SCPI
command may not execute correctly
depending on the status of this product.
5 32 Command Error (CME)
This bit is set when an IEEE 488.2 syntax
error is detected by the syntax analysis
system, an unrecognizable header is
received, or a group execution trigger is input
into the input buffer in the IEEE 488.2 SCPI
command.
6 64 User Request (URQ) Not used
7 128 Power ON (PON) Not used
8-15 Reserved Not used