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PC Cards cifX Compact PCI, Mini PCI, Mini PCIe, PCI-104 | Installation, Operation and Hardware Description
DOC120205UM53EN | Revision 53 | English | 2019-03 | Released | Public
© Hilscher, 2008-2019
9.12.4 Pin Assignment for Mini PCI Express Bus / SYNC Connector
(Bootstart), X1/X2
Only for Hardware Revision B:
CIFX 90E-RE\F*, CIFX 90E-RE\F\M12*, CIFX 90E-
DP\F, CIFX 90E-CO\F, CIFX 90E-DN\F, CIFX 90E-RE\MR\F*, CIFX 90E-RE\MR\F\M12*,
CIFX 90E-DP\MR\F, CIFX 90E-CO\MR\F, CIFX 90E-DN\MR\F,
And for Hardware Revison 1:
CIFX 90E-RE\NHS\F*, CIFX 90E-RE\NHS\F\M12*, CIFX
90E-DP\NHS\F, CIFX 90E-CO\NHS\F, CIFX 90E-DN\NHS\F, CIFX 90E-CC\NHS\F, CIFX
90E-RE\ET\F*, CIFX 90E-RE\ET\F\M12*, CIFX 90E-DP\ET\F, CIFX 90E-CO\ET\F, CIFX
90E-DN\ET\F, CIFX 90E-CC\ET\F, CIFX 90E-RE\MR\ET\F*, CIFX 90E-RE\MR\ET\F\M12*,
CIFX 90E-DP\MR\ET\F, CIFX 90E-CO\MR\ET\F, CIFX 90E-DN\MR\ET\F, CIFX 90E-
CC\MR\ET\F
*The SYNC connection is realized via the mini PCI Express bus.
Pin (X1) Signal Pin (X2) Signal
51 (not used) 52 +3.3V
49 (not used) 50 GND
47 (not used) 48 (not used)
45 (not used) 46 IO_SYNC0 ( not used with fieldbus protocols )
43 GND 44 IO_SYNC1 ( not used with fieldbus protocols )
41 +3.3V 42 Bootstart
39 (not used) 40 GND
37 GND 38 USB_D+ ( disabled – not used )
35 GND 36 USB_D - ( disabled – not used )
33 PERp0
8
34 GND
31 PERn0
8
32 (not used)
29 GND 30 (not used)
27 GND 28 (not used)
25 PETp0
8
26 GND
23 PETn0
8
24 (not used)
21 GND 22 PERST#
19 (not used) 20 (not used)
17 (not used) 18 GND
15 GND 16 (not used)
13 14 (not used)
11 REFCLK- 12 (not used)
9 GND 10 (not used)
7 CLKREQ# 8 (not used)
5 (not used) 6 (not used)
3 (not used) 4 GND
1 (not used) 2 3.3V
Table 129: Pin Assignment Mini PCI Express Bus / SYNC Connector, X1/X2
Unless otherwise noted, the pin assignment for Mini PCI Express bus,
X1/X2 described in
Table 129 corresponds to the bus specification for Mini
PCI Express [bus spec 6, Rev. 1.2, Section 3.3].
Note! Note the following characteristics for the pin assignment of the Mini PCI
Express Bus, X1/X2, described in Table 129 :
ƒ The Pins 6, 28, 48 and Pin 24 are ‘not used’ .
ƒ The Pins 36 and 38 are ‘not used’ .
ƒ
The pin assignment of the Pins 42, 44, 46 deviates from the standard
specification Mini PCI Express.
8
The names of the pins 33 and 31 with PER (,R’ for ,Receive') and of the pins 25 and 23 with PET ('T'
for,Transmit') are defined in the view of the PC card cifX. The names in the bus specification are defined
from the perspective of the host.