Fluke 9100 Series, Руководство пользователя

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Section 6: 9100 System Operation — SCPI Language 6-21
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Bit 5 Command Error (CME)
CME occurs when a received bus command does not satisfy the IEEE 488.2 generic
syntax or the device command syntax programmed into the instrument interface’s parser,
and so is not recognized as a valid command. The appropriate error message is added to
the Error Queue. See the 'Note about the Error Queue' on the previous page.
Bit 6 User Request (URQ)
This bit is not used in the 9100. It is always set false.
Bit 7 9100 Power Supply On (PON)
This bit is set true only when the Line Power has just been switched on to the 9100, the
subsequent Power-up Selftest has been completed successfully, and the 9100 defaults
into Manual mode at Power-on. (If the Power-on default is Procedure mode, remote
operation is not available. If the selftest is unsuccessful, the 9100 will report the fact in
Test mode, which also does not permit remote operation).
Whether or not an SRQ is generated by setting bit 7 true, depends on the previously-
programmed ‘Power On Status Clear’ message
∗
PSC phs Nrf:
• For an Nrf of 1, the Event Status Enable register would have been cleared at power on,
so PON would not generate the ESB bit in the Status Byte register, and no SRQ would
occur at power on.
• If Nrf was zero, and the Event Status Enabling register bit 7 true, and the Service
Request Enabling register bit 5 true; a change from Power Off to Power On will
generate an SRQ. This is only possible because the enabling register conditions are
held in non-volatile memory, and restored at power on.
This facility is included to allow the application program to set up conditions so that a
momentary Power Off followed by reversion to Power On (which could upset the 9100
programming) will be reported by SRQ. To achieve this, the Event Status register bit 7
must be permanently true (by
∗
ESE phs Nrf, where Nrf
≥
128); the Status Byte Enable
register bit 5 must be set permanently true (by command
∗
SRE phs Nrf, where Nrf lies
in one of the ranges 32-63, 96-127, 160-191, or 224-255); Power On Status Clear must
be disabled (by
∗
PSC phs Nrf, where Nrf = 0); and the Event Status register must be read
destructively immediately following the Power On SRQ (by the common query
∗
ESR?).
Continued Overleaf