6-20
Section 6: 9100 System Operation — SCPI Language
Final Width = 215mm
6.5.3.5
IEEE 488.2-defined Event Status Register
The ‘Event Status Register’ holds the Event Status Byte, consisting of event bits, each of
which directs attention to particular information. All bits are ‘sticky’; ie. once true,
cannot return to false until the register is cleared. This occurs automatically when it is read
by the query:
∗
ESR?. The common command
∗
CLS clears the Event Status Register and
associated error queue, but not the Event Status Enable Register.
Note that because the bits are 'sticky', it is necessary to read the appropriate subordinate
register of the status structure in order to clear its bits and allow a new event from the same
source to be reported.
The ‘Event Status Register’ bits are named in mnemonic form as follows:
Bit 0 Operation Complete (OPC)
This bit is true only if
∗
OPC has been programmed and all selected pending operations
are complete. As the 9100 operates in serial mode, its usefulness is limited to registering
the completion of long operations, such as self-test.
Bit 1 Request Control (RQC)
This bit is not used in the 9100. It is always set false.
Bit 2 Query Error (QYE)
QYE true indicates that the application program is following an inappropriate message
exchange protocol, resulting in the following situations:
•
Interrupted Condition. When the 9100 has not finished outputting its Response
Message to a Program Query, and is interrupted by a new Program Message.
•
Unterminated Condition. When the application program attempts to read a Response
Message from the 9100 without having first sent the complete Query Message
(including the Program Message Terminator) to the instrument.
•
Deadlocked Condition. When the input and output buffers are filled, with the parser
and the execution control blocked.
Bit 3 Device Dependent Error (DDE)
DDE is set true when an internal operating fault is detected, and the appropriate error
message is added to the Error Queue. See the 'Note about the Error Queue' in the previous
column.
Bit 4 Execution Error (EXE)
An execution error is generated if the received command cannot be executed, owing to
the device state or the command parameter being out of bounds. The appropriate error
message is added to the Error Queue. See the 'Note about the Error Queue' in the previous
column.
Note about the ERROR Queue
The Error Queue is a sequential
memory stack. Each reportable error
has been given a listed number and
explanatory message, which are entered
into the error queue as the error occurs.
The queue is read destructively as a
First-In/First-Out stack, using the query
command SYSTem ERRor? to obtain
a code number and message.
Repeated use of the query SYSTem
ERRor? will read successive Device-
Dependent, Command and Execution
errors until the queue is empty, when
the 'Empty' message (
0,"No error"
)
will be returned.
It would be good practice to repeatedly
read the Error Queue until the 'Empty'
message is returned.
The common command
∗
CLS clears
the queue.
Содержание 9100 Series
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