6-54
IM 701310-01E
• Example
This example displays the data sequence at the byte level (hexadecimal notation) and
indicates the trigger position. The following notations are used in the figure.
S: Start condition, P: Stop condition, Shading: Compared pattern
Trigger on a start byte
Mode
Start Byte/HS Mode
Type
Start byte
S
Sr
AE
57
27
FE
98
99
27
P
Triggers here
Sr: Restart
01
SDA, SCL, and Qualification
SDA and SCL Sources
You can select the SDA (serial data) and SCL (serial clock) sources from CH1 to CH4.
Trigger Level
You can set the I
2
C bus signal trigger level for CH1 to CH4 separately.
• The selectable range is 8 divisions within the screen. The resolution is 0.01 divisions.
For example, if the T/div setting is 2 mV/division, the resolution is 0.02 mV.
• You can reset the trigger level to the current offset voltage by pressing RESET.
Hysteresis
See section 6.5 for details.
Qualification and Logic
• Qualification
Set the state of signals other than those selected for the SDA and SCL to H, L, or
X. This trigger requirement is called qualification requirement. The qualification
requirement is met when the selected state matches the input signal state.
H
When the input signal is high
L
When the input signal is low
X
Not used as a trigger condition (Don’t care)
* The level for determining high or low is the trigger level that you set above when you set the
signal to a channel from CH1 to CH4.
6.15 Triggering on an I
2
C Bus Signal
