Table 53: BAR Size Ranges for Device Configuration
PCIe Device / Port Type
BAR Type
BAR Size Range
PCI Express Endpoint
32-bit Memory
128 bytes (B) – 2 gigabytes (GB)
64-bit Memory
128 B – 8 Exabytes
Legacy PCI Express Endpoint
32-bit Memory
128 B – 2 GB
64-bit Memory
128 B – 8 Exabytes
I/O
16 B – 2 GB
• Prefetchable: Identifies the ability of the memory space to be prefetched.
• Value: The value assigned to the BAR based on the current selections.
• Expansion ROM Base Address Register: If selected, the Expansion ROM is activated and can
be sized from 2 KB to 4 GB. According to the PCI Local Bus Specification Revision 3.0 on the
, the maximum size for the Expansion ROM BAR should be no larger than 16
MB. Selecting an address space larger than 16 MB can cause compliance testing issues.
• Managing Base Address Register Settings: Memory, I/O, Type, and Prefetchable settings are
handled by setting the appropriate settings for the desired base address register.
Memory or I/O settings indicate whether the address space is defined as memory or I/O. The
base address register only responds to commands that access the specified address space.
Generally, memory spaces less than 4 KB in size should be avoided. The minimum I/O space
allowed is 16 bytes; use of I/O space should be avoided in all new designs.
Prefetchability is the ability of memory space to be prefetched. A memory space is
prefetchable if there are no side effects on reads (that is, data is not destroyed by reading, as
from a RAM). Byte-write operations can be merged into a single double word write, when
applicable.
When configuring the core as an Endpoint for PCIe (non-Legacy), 64-bit addressing must be
supported for all BARs (except BAR5) that have the prefetchable bit set. 32-bit addressing is
permitted for all BARs that do not have the prefetchable bit set. The prefetchable bit-related
requirement does not apply to a Legacy Endpoint. The minimum memory address range
supported by a BAR is 128 bytes for a PCI Express Endpoint and 16 bytes for a Legacy PCI
Express Endpoint.
• Disabling Unused Resources: For best results, disable unused base address registers to
conserve system resources. A base address register is disabled by deselecting unused BARs in
the Customize IP dialog box.
• Copy PF0: When set, the Copy PF0 option allows you to set all BARs settings of the remaining
PFs to the same values as PF0. Applicable when there are more than one total Physical
Function (PF).
Chapter 5: Design Flow Steps
PG346 (v3.3) November 16, 2022
CPM Mode for PCI Express
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