Table 28: Requester Completion Interface Port Descriptions (1024-bit Interface)
(cont'd)
Name
I/O
Width
Description
pcie0_m_axis_rc_tlast
pcie1_m_axis_rc_tlast
O
1
The core asserts this signal in the last beat of a packet to
indicate the end of the packet. When a TLP is transferred
in a single beat, the core sets this bit in the first beat of
the transfer. This output is used only when the straddle
option is disabled. When the straddle option is enabled,
the core sets this output permanently to 0.
pcie0_m_axis_rc_tkeep
pcie1_m_axis_rc_tkeep
O
32
The assertion of bit i of this bus during a transfer
indicates to the user logic that Dword i of the
pcie(n)_m_axis_rc_tdata bus contains valid data. The core
sets this bit to 1 contiguously for all Dwords starting from
the first Dword of the descriptor to the last Dword of the
payload. Thus, pcie(n)_m_axis_rc_tkeep is set to all 1s in all
beats of a packet, except in the final beat when the total
size of the packet is not a multiple of the width of the data
bus (both in Dwords). This is true for both Dword-aligned
and address-aligned modes of payload transfer.
These outputs are permanently set to all 1s when the
straddle option is enabled. The user logic must use the
signals in pcie(n)_m_axis_rc_tuser in that case to
determine the start and end of Completion TLPs
transferred over the interface.
pcie0_m_axis_rc_tvalid
pcie1_m_axis_rc_tvalid
O
1
The core asserts this output whenever it is driving valid
data on the pcie(n)_m_axis_rc_tdata bus. The core keeps
the valid signal asserted during the transfer of a packet.
The user application can pace the data transfer using the
pcie(n)_m_axis_rc_tready signal.
pcie0_m_axis_rc_tready
pcie1_m_axis_rc_tready
I
1
Activation of this signal by the user logic indicates to the
PCIe core that the user logic is ready to accept data. Data
is transferred across the interface when both
pcie(n)_m_axis_rc_tvalid and pcie(n)_m_axis_rc_tready are
asserted in the same cycle.
If the user logic deasserts the ready signal when the valid
signal is High, the core maintains the data on the bus and
keep the valid signal asserted until the user logic has
asserted the ready signal.
Table 29: Sideband Signals in pcie(n)_m_axis_rc_tuser (1024-bit Interface)
Bit Index
Name
Width
Description
127:0
byte_en
127
The client logic may optionally use these byte enable bits to
determine the valid bytes in the payload of a packet being
transferred. The assertion of bit i of this bus during a
transfer indicates to the client that byte i of the
pcie(n)_m_axis_cq_tdata bus contains a valid payload byte.
This bit is not asserted for descriptor bytes.
Although the byte enables can be generated by client logic
from information in the request descriptor (address and
length), the client has the option of using these signals
directly instead of generating them from other interface
signals. The 1 bits in this bus for the payload of a TLP are
always contiguous.
Chapter 3: Product Specification
PG346 (v3.3) November 16, 2022
CPM Mode for PCI Express
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