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Xilinx Versal ACAP CPM4, Product Manual

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CCIX Transaction Layer

The Cache Coherent Interconnect for Accelerators (CCIX) transaction layer requirements are
implemented by the optional virtual channel 1 (VC1) in the design. Note that VC1 storage is in
addition to the PCI Express-compliant virtual channel 0 (VC0) storage. The CCIX transaction layer
interfaces with the CCIX protocol layer is implemented externally to the PCIe ports over the
CCIX transaction layer (ARM CXS) hard interface. For more information, see the Versal ACAP CPM
CCIX Architecture Manual (

AM016

).

Data Link Layer

The data link layer acts as an intermediate stage between the transaction layer and the physical
layer. Its primary responsibility is to provide a reliable mechanism for the exchange of information
between two components on a link. This includes data exchange (TLPs), error detection and
recovery, initialization services and the generation and consumption of data link layer packets
(DLLPs). DLLPs are used to transfer information between data link layers of two directly
connected components on the link. DLLPs convey information, such as power management, flow
control, and TLP acknowledgments. The data link layer supports 32 kilobyte replay buffers and
the feature DLLP.

Physical Layer

The physical layer interfaces the data link layer with signaling technology for link data
interchange, and is subdivided into the logical sub-block and the electrical sub-block.

• The logical sub-block frames and de-frames TLPs and DLLPs. It also implements the link

training and status state machine (LTSSM), which handles link initialization, training, and
maintenance. Scrambling and descrambling of data (for Gen1/Gen2/Gen3/Gen4 operation) is
also performed in this sub-block.

• The electrical sub-block defines the input and output buffer characteristics that interface the

device to the PCIe link. The physical layer also supports lane reversal (for multi-lane designs)
and lane polarity inversion, as required by the PCI Express Base Specification 4.0 (

https://

www.pcisig.com/specifications

).

Data exchange with the other components on the link occurs over the serial lines of one or more
gigabit transceivers (GTs), which expose parallel interfaces at lower clock frequencies to the PCIe
controller. For Gen1, Gen2, Gen3 and Gen4 operation, the physical layer is up-configuration
capable in the downstream port mode only.

Standards

The CPM4 block adheres to the following standards:

• PCI Express Base Specification 4.0 Version 1.0, and Errata updates (available at 

http://

pcisig.com/specifications

).

Chapter 1: Overview

PG346 (v3.3) November 16, 2022

 

www.xilinx.com

CPM Mode for PCI Express

 8

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Summary of Contents for Versal ACAP CPM4

Page 1: ...ing non inclusive language from our products and related collateral We ve launched an internal initiative to remove language that could exclude people or reinforce historical biases including terms em...

Page 2: ...g Tandem PCIe for Stage 2 32 Known Issues and Limitations 36 Chapter 3 Product Specification 38 Performance 38 Minimum Device Requirements 39 Port Descriptions 40 Register Space 122 Chapter 4 Designin...

Page 3: ...Help on Xilinx com 253 PCIe Link Debug Enablement 254 Appendix D Using the High Speed Debug Port Over PCIe for Design Debug 261 Overview 261 Implementing the HSDP over PCIe Example Design 268 Appendix...

Page 4: ...rm and developing the application code using the embedded CPU Also covers XRT and Graph APIs The topic in this document that applies to this design process include Register Space Host Software Develop...

Page 5: ...urces in the programmable logic All feature references are applicable to both instances of CPM4 PCIe controllers with the following exceptions CPM4 PCIe Controller 0 supports up to x16 operation and C...

Page 6: ...16b 250 MHz Gen3 8 0 GT s 16b 500 MHz Gen4 16 0 GT s 32b 500 MHz Transaction Layer VC0 CCIX VC1 PCIe Core Clock In PCIe Reset In Global Event Inputs XPIPEIM Misc Port 512b 512b AXI4 MM Bridge DMA AXI...

Page 7: ...ed as a Xilinx specific streaming protocol implementation and run on top of the industry standard AXI4 Stream interface The CPM4 PCIe controllers support management of up to 256 extended tag or 768 10...

Page 8: ...LP Physical Layer The physical layer interfaces the data link layer with signaling technology for link data interchange and is subdivided into the logical sub block and the electrical sub block The lo...

Page 9: ...eight traffic classes One CCIX compliant virtual channel Support for multiple functions and Single Root IO Virtualization SR IOV Up to 4 physical functions Up to 252 virtual functions PASID Prefix ca...

Page 10: ...BAR and ID based filtering of received transactions Optional ASPM support for endpoint port types only ASPM is not supported for other port types Configuration extend interface AXI4 Stream interfaces...

Page 11: ...Global Event Inputs XPIPEIM 512b Init Ctrl XPIPE Static Switch PS Internal Hard I F Programming Register Space 512b 512b cfg 512b 32b attr_ 0 dbg_0_0 dbg_0_1 attr_dma_ Enhanced AXI4 ST CFG Fabric I F...

Page 12: ...ts 256 bits 512 bits and 1024 bits Transaction Layer The transaction layer is the upper layer of the PCI Express architecture and its primary function is to accept buffer and forward transaction layer...

Page 13: ...nce Scrambling and descrambling of data for Gen1 Gen2 Gen3 Gen4 Gen5 operation is also performed in this sub block The electrical sub block defines the input and output buffer characteristics that int...

Page 14: ...rted in PCI Express and EDR PHY Modes PCI Express Support Gen4x4 Gen4x8 Gen4x16 Gen5x4 Gen5x8 EDR Support x4 and x8 link width capability AXI4 Stream Interfaces to Programmable Logic PL Configurable 6...

Page 15: ...s AXI4 Streaming TLP Straddle on Requester Completion Interface Up to 1024 RX Completion Header Credits and 64 KB RX Completion Payload Space Relaxed Transaction Ordering in the Receive Data Path Addr...

Page 16: ...is to construct a bus mastering Endpoint using a CPM PCIe controller This use model is applicable to most applications that interface the Endpoint port on the ACAP on an add in card to a root complex...

Page 17: ...ering DMA Logic Bridge to User Application M e m R d Mem Rd Wr Control Status Registers RX CplD PCIe CPM PCIe Controller CONTROL LOGIC Mem Rd Mem Wr D E M U X C p l D CplD Completer Interfaces Request...

Page 18: ...access and control two distinct applications independently The user logic implements the DMA control registers and applications Figure 4 Illustrative Example of Two Function Endpoint Use Case FUN0 App...

Page 19: ...ons and minimizes the soft logic requirement to implement an SR IOV Endpoint Figure 5 Illustrative Example of Endpoint with SR IOV Use Case VM1 VM0 VF0 CPM PCIe Controller DMA Control Regs TX Buf RX B...

Page 20: ...m a small external ROM so as to meet the 100 ms configuration requirement A PCIe link is formed with a Root Complex or Switch component which is subsequently used to download the design that configure...

Page 21: ...O SCU Snoop Control Unit L2 Cache Memory 256 KB Core Switch OCM On Chip Memory 256 KB DMA 8 channel Mem Switch DDR Memory Controller DDR2 DDR3 LPDDR2 16 bit 32 bit 16 bit w ECC AXGM x 2 General Purpo...

Page 22: ...Mode for PCIe visit the Versal ACAP CPM Mode for PCIe product web page Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page For information about pr...

Page 23: ...e device Two variants are supported Tandem PROM Loads both stages from a single programming image from a standard primary boot interface Tandem PCIe Loads the first stage from a primary boot interface...

Page 24: ...bitstream data to the PMC allows for high throughput and minimal design requirements and is simplified by provided software and drivers Note Tandem and DFX features are not supported together in a sin...

Page 25: ...f the design the design must include connectivity from the enable CPM Master s to the PMC Slave This should be accomplished through the block design connectivity note that when PCIe Controller 0 is se...

Page 26: ...ption to Advanced 2 Under the Advanced Options tab check the box for MCAP Capability IMPORTANT The MCAP VSEC can only natively address the lower 4 GB of the address map as it can only issue 32 bit add...

Page 27: ...nformation on Tandem PCIe using QDMA or XDMA see Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide PG347 To deliver stage 2 images using PCIe DMA the DMA BAR must be set to BAR0 The dr...

Page 28: ...sign_1_wrapper_tandem2 rcdo Writing NPI partition design_1_wrapper_tandem2 rnpi Writing NPI partition design_1_wrapper_shutdown txt Generating bif file design_1_wrapper_tandemPROM bif for Tandem PROM...

Page 29: ...ation is not supported for part device IMPORTANT Do NOT use this solution on engineering silicon ES1 for VC1902 VC1802 or VM1802 devices In UltraScale the Field Updates solution enables you to build R...

Page 30: ...c application These are enumerated below QDMA MM Data Path If the QDMA Memory Mapped data path is enabled it can be used to download through PCIe into the FPGA Slave Boot Interface at a maximum rate o...

Page 31: ...ding on the delivery path and PCIe controller options configuration performance can be up to 3 2 GB s while configuring the programmable logic CPM QDMA MM to SBI Gen3x16 maximum expected bandwidth 3 2...

Page 32: ...SBI would require the use of soft IP or the Versal MCAP VSEC CPM5 does not support the use of the XDMA controller Table 1 Bitstream Delivery Details from PCIe to SBI Delivery Method CPM4 HW Capable C...

Page 33: ...ake TANDEM_BOOT_SUPPORTED 1 3 Copy driver and application executables to standard destinations a make install 4 Generate the qdma conf file manually or using the qdma_generate_conf_file sh script and...

Page 34: ...wing recommended command as an example to employ remapping from 32 bit address space to 48 bit address space for the SBI buffer set_property CONFIG REMAPS M00_AXI 0xF122_0000 0x1_0122_0000 64K 0xF210_...

Page 35: ...BI buffer as demonstrated in the important note above Tandem Configuration Example Design A set of example designs are hosted on GitHub in the XilinxCEDStore repository These repositories can be acces...

Page 36: ...PCIe features incompatible with Tandem Configuration PCIe Extended Configuration Space as this requires PL logic QDMA multi function is not supported This feature uses PL mailbox which will be probed...

Page 37: ...as well as insertion of any decoupling logic are the responsibility of the designer The dynamic DFX portion of the solution would be limited to programmable logic and NoC resources and not parts of th...

Page 38: ...X8 X8 X16 1000 781 25 390 625 3E 3HP E 0 to 110 Vhp 0 88 X16 X16 X16 X16 X8 X8 X16 1000 781 25 390 625 1E 1MP E 0 to 100 Vmp 0 78 X16 X16 X16 X8 NA NA X8 1000 500 250 1I 1MP I 40 to 110 Vmp 0 78 X16...

Page 39: ...10 Vmp 0 78 X8 X8 X8 X8 NA NA X8 500 500 250 2I 2MP I 40 to 110 Vmp 0 78 X8 X8 X8 X8 X8 X8 X8 781 25 781 25 390 625 2HP I 40 to 110 Vhp 0 88 X8 X8 X8 X8 X8 X8 X8 781 25 781 25 390 625 1Q 1MQ derated Q...

Page 40: ...x16 x16 Gen3 8 GT s per lane x16 x16 x16 x16 x16 x16 x16 x16 Gen4 16 GT s per lane x8 x8 x8 x162 x8 x162 x162 x162 Gen5 32 GT s per lane 3 N A N A N A x82 N A x82 x82 x82 Notes 1 See Versal Premium S...

Page 41: ...a pcie1_m_axis_cq_tdata O DW Transmit Data from the CQ Interface Only the lower 128 bits are used when the interface width is 128 bits and only the lower 64 bits are used when the interface width is 6...

Page 42: ...terface when both pcie n _m_axis_cq_tvalid and pcie n _m_axis_cq_tready are asserted in the same cycle If the user application deasserts the ready signal when pcie n _m_axis_cq_tvalid is High the core...

Page 43: ...his field reflects the setting of the First_BE bits in the Transaction Layer header of the TLP For Memory Reads and I O Reads these four bits indicate the valid bytes to be read in the first Dword For...

Page 44: ...op 1 Start of packet This signal is asserted by the core in the first beat of a packet to indicate the start of the packet Using this signal is optional 41 discontinue 1 This signal is asserted by the...

Page 45: ...ion must assert this signal in the last cycle of a packet to indicate the end of the packet When the TLP is transferred in a single beat the user application must set this bit in the first cycle of th...

Page 46: ...latter case the core treats the error as sticky for the following beats of the packet even if the user application deasserts the discontinue signal before the end of the packet The discontinue signal...

Page 47: ...d in a single beat the user application must set this bit in the first cycle of the transfer pcie0_s_axis_rq_tkeep pcie1_s_axis_rq_tkeep I DW 32 TKEEP Indication for Requester reQuest Data The asserti...

Page 48: ...eQuest TLP transmit sequence number valid This output is asserted by the core for one cycle when it has placed valid data on pcie n _rq_seq_num0 3 0 pcie0_rq_tag0 pcie0_rq_tag1 pcie1_rq_tag0 pcie1_rq_...

Page 49: ...eing transferred The core samples this field in the first beat of a packet when pcie n _s_axis_rq_tvalid and pcie n _s_axis_rq_tready are both High When the requester request interface is configured i...

Page 50: ...4 bits When an interface parity error is detected it is recorded as an uncorrectable internal error and the packet is discarded According to the Base Spec 6 2 9 PCI SIG Specifications https www pcisig...

Page 51: ...pcie1_m_axis_rc_tkeep O DW 32 TKEEP indication for Requester Completion Data The assertion of bit i of this bus during a transfer indicates that Dword i of the pcie n _m_axis_rc_tdata bus contains va...

Page 52: ...and bits 31 8 are set permanently to 0 when the interface width is configured as 64 bits The byte enable bit is also set on completions received in response to zero length memory read requests 32 is_...

Page 53: ...h the signals is_eof_0 0 and is_sof_1 are also High in the same beat 42 discontinue 1 This signal is asserted by the core in the last beat of a TLP if it has detected an uncorrectable error while read...

Page 54: ...l beats of a packet except in the final beat when the total size of the packet is not a multiple of the width of the data bus both in Dwords This is true for both Dword aligned and 128b address aligne...

Page 55: ...ycle based on the status of its Non Posted request receive buffer or can set it to 11 permanently if it does not need to exercise selective backpressure on Non Posted requests The setting of pcie_cq_n...

Page 56: ...id bytes in the ending Dword of the payload For Memory Reads and Writes of one DW transfers and zero length transfers these bits should be 0s For Atomic Operations and Messages with a payload these bi...

Page 57: ...ting in this beat 10 Byte lane 32 00 01 11 Reserved This output is used only when the straddle option is enabled on the CQ interface The core can then straddle two TLPs in the same beat The output is...

Page 58: ...d for packet0 226 Execute Requested 1 1 Indicates Execute Requested for packet1 227 Privileged Mode Requested 0 1 Indicates Privileged Mode Requested for packet0 to the user design 228 Privileged Mode...

Page 59: ...cket The core paces the data transfer using the pcie n _s_axis_cc_tready signal pcie0_s_axis_cc_tready pcie1_s_axis_cc_tready O 4 Activation of this signal by the PCIe core indicates that it is ready...

Page 60: ...ngs are as follows 00 No TLPs ending in this beat 01 A single TLP is ending in this beat is_eop0_ptr 3 0 provides the offset of the last Dword of this TLP 11 Two TLPs are ending in this beat is_eop0_p...

Page 61: ...Error Reporting AER 80 17 parity 64 Odd parity for the 256 bit data When parity checking is enabled in the core user logic must set bit i of this bus to the odd parity computed for byte i of pcie n _...

Page 62: ...ignal asserted during the transfer of a packet The core paces the data transfer using the pcie n _s_axis_rq_tready signal pcie0_s_axis_rq_tready pcie1_s_axis_rq_tready 4 O Activation of this signal by...

Page 63: ...1_rq_seq_num0 6 O The user may optionally use this output to keep track of the progress of the request in the core s transmit pipeline To use this feature the user application must provide a sequence...

Page 64: ...te enables for the second TLP starting in this beat if present For Memory Reads and Writes of one DW transfers and zero length transfers these bits should be 0s For Memory Reads of 2 Dwords or more th...

Page 65: ...second TLP starting in this beat 10 Byte lane 32 00 01 11 Reserved This output is used only when the straddle option is enabled on the interface 27 26 is_eop 1 0 2 Signals that a TLP is ending in this...

Page 66: ...the progress of the request in the core s transmit pipeline The core outputs this sequence number on its pcie n _rq_seq_num0 or pcie n _rq_seq_num1 output when the request TLP has progressed to a poin...

Page 67: ...Indicates Execute Requested 0 180 Execute Requested 1 1 Indicates Execute Requested 1 181 Privileged Mode Requested 0 1 Indicates Privileged Mode Requested 0 182 Privileged Mode Requested 1 1 Indicat...

Page 68: ...fer using the pcie n _m_axis_rc_tready signal pcie0_m_axis_rc_tready pcie1_m_axis_rc_tready I 1 Activation of this signal by the user logic indicates to the PCIe core that the user logic is ready to a...

Page 69: ...start position of the first TLP is_sop1_ptr 1 0 provides the start position of the second TLP is_sop2_ptr 1 0 provides the start position of the third TLP and is_sop3_ptr 1 0 provides the start positi...

Page 70: ...cond TLP 0111 Three TLPs are ending in this beat is_eop0_ptr 3 0 provides the offset of the last Dword of the first TLP is_eop1_ptr 3 0 provides the offset of the last Dword of the second TLP and is_e...

Page 71: ...configured as an Endpoint the error is also reported by the core to the Root Complex it is attached to using Advanced Error Reporting AER 160 97 parity 64 Odd parity for the 512 bit transmit data Bit...

Page 72: ...the user logic is ready to accept data Data is transferred across the interface when both pcie n _m_axis_cq_tvalid and pcie n _m_axis_cq_tready are asserted in the same cycle If the user logic deasse...

Page 73: ...se these byte enable bits to determine the valid bytes in the payload of a packet being transferred The assertion of bit i of this bus during a transfer indicates to the user logic that byte i of the...

Page 74: ...cie n _m_axis_cq_tvalid and is_sop 3 are both asserted High 159 144 last_be 15 0 16 Byte enables for the last Dword of the payload last_be 3 0 reflects the setting of the Last Byte Enable bits in the...

Page 75: ...spectively 1111 Three TLPs are starting in this beat at locations determined by is_sop0_ptr 1 0 is_sop1_ptr 1 0 is_sop_2_ptr 1 0 and is_sop2_ptr 1 0 respectively All other values are reserved Use of t...

Page 76: ...This output is valid when is_eop 0 is asserted 185 181 is_eop1_ptr 4 0 5 Offset of the last Dword of the second TLP ending in this beat This output is valid when is_eop 1 is asserted The output is per...

Page 77: ...tion is enabled the core ignores the setting of this input using instead the is_sop is_eop signals in the pcie n _s_axis_cc_tuser bus to determine the start and end of TLPs pcie0_s_axis_cc_tkeep pcie1...

Page 78: ...s indicated by is_sop0_ptr 1 0 0011 Two new TLPs are starting in this beat is_sop0_ptr 1 0 provides the start position of the first TLP and is_sop1_ptr 1 0 provides the start position of the second TL...

Page 79: ...of the last Dword of the first TLP is_eop1_ptr 4 0 provides the offset of the last Dword of the second TLP is_eop2_ptr 4 0 provides the offset of the last Dword of the third TLP and is_eop3_ptr 4 0 pr...

Page 80: ...d Error Reporting AER 164 137 parity 128 Odd parity for the data When parity checking is enabled in the core user logic must set bit i of this bus to the odd parity computed for byte i of pcie n _s_ax...

Page 81: ...ignal asserted during the transfer of a packet The core paces the data transfer using the pcie n _s_axis_rq_tready signal pcie0_s_axis_rq_tready pcie1_s_axis_rq_tready 1 O Activation of this signal by...

Page 82: ...r one cycle when pcie n _rq_tag_vld1 is asserted pcie0_rq_seq_num0 pcie1_rq_seq_num0 6 O The user may optionally use this output to keep track of the progress of the request in the core s transmit pip...

Page 83: ...nd TLP in this beat last_be 11 8 reflects the setting of the Last Byte Enable bits in the Transaction Layer header of the third TLP in this beat and last_be 15 12 reflects the setting of the Last Byte...

Page 84: ...tr 1 0 is_sop_2_ptr 1 0 and is_sop3_ptr 1 0 respectively All other values are reserved Use of this signal is optional for the user logic when the straddle option is not enabled because a new TLP alway...

Page 85: ...of the second TLP ending in this beat This output is valid when is_eop 1 is asserted 78 74 is_eop2_ptr 4 0 5 Offset of the last Dword of the third TLP ending in this beat This output is valid when is_...

Page 86: ...q_tready are both high This input can be hardwired to 0 when the user logic is not monitoring the pcie n _rq_seq_num outputs of the core 360 355 seq_num1 5 0 6 If there is a second TLP starting in the...

Page 87: ...ut whenever it is driving valid data on the pcie n _m_axis_rc_tdata bus The core keeps the valid signal asserted during the transfer of a packet The user application can pace the data transfer using t...

Page 88: ...1 0 provides the start position of the second TLP is_sop2_ptr 1 0 provides the start position of the third TLP and is_sop3_ptr 1 0 provides the start position of the fourth TLP 00011111 Five TLPs star...

Page 89: ...111 Byte lane 112 All other settings are reserved 144 142 is_sop2_ptr 2 0 3 Indicates the position of the first byte of the third TLP starting in this beat 010 Byte lane 32 011 Byte lane 48 100 Byte...

Page 90: ...t is used only when the straddle option is enabled on the RC interface The output is permanently set to 0 when straddle is disabled 156 154 is_sop6_ptr 2 0 Indicates the position of the first byte of...

Page 91: ...d by is_eop0_ptr 4 0 is_eop1_ptr 4 0 is_eop2_ptr 4 0 is_eop3_ptr 4 0 and is_eop4_ptr 4 0 respectively 00111111 Six TLPs ending in this beat at locations determined by is_eop0_ptr 4 0 is_eop1_ptr 4 0 i...

Page 92: ...ion is enabled on the RC interface The output is permanently set to 0 when straddle is disabled 207 203 is_eop7_ptr 4 0 5 Offset of the last Dword of the eigth TLP ending in this beat This output is v...

Page 93: ...gement interface of the core Note The pcie0 signals map to PCIe Controller 0 and pcie1 signals map to PCIe Controller 1 in the port descriptions below Table 31 Configuration Management Interface Port...

Page 94: ...nes the ports in the Configuration Status interface of the core Note The pcie0 signals map to PCIe Controller 0 and pcie1 signals map to PCIe Controller 1 in the port descriptions below Table 32 Confi...

Page 95: ...7 down to 5 This field sets the maximum TLP payload size As a Receiver the logic must handle TLPs as large as the set value As a Transmitter the logic must not generate TLPs exceeding the set value 00...

Page 96: ...11 Function 2 INTx Disable Bit 12 Function 3 I O Space Enable Bit 13 Function 3 Memory Space Enable Bit 14 Function 3 Bus Master Enable Bit 15 Function 3 INTx Disable pcie0_cfg_vf_status pcie1_cfg_vf_...

Page 97: ...unction 0 and bits 5 3 capture that of virtual function 1 and so on The possible power states are 000 D0_uninitialized 001 D0_active 010 D1 100 D3_hot Other values are reserved pcie0_cfg_link_power_st...

Page 98: ...orrectable ECC Error Priority 1 01011b Receive Completion RAM Correctable ECC Error Priority 21 01100b Receive Completion RAM Uncorrectable ECC Error Priority 2 01101b Receive Posted Buffer Overflow E...

Page 99: ...Do not rely solely on this signal to indicate an error Alternatively you can decode AER register to accurately detect errors pcie0_cfg_rx_pm_state pcie1_cfg_rx_pm_state O 2 Current RX Active State Pow...

Page 100: ...oopback_Active_Master 23 Loopback_Exit_Master 24 Loopback_Entry_Slave 25 Loopback_Active_Slave 26 Loopback_Exit_Slave 27 Hot_Reset 28 Recovery_Equalization_Phase0 29 Recovery_Equalization_Phase1 2a Re...

Page 101: ...tatus of this interrupt can be read from the Link Equalization Request bit of the Link Status 2 register The pl_interrupt output is not active when the core is configured as an Endpoint pcie0_cfg_ext_...

Page 102: ...cie0_cfg_msg_received assertion and the parameters transferred on cfg_msg_data 7 0 in each cycle for each type of message The core inserts at least a one cycle gap between two consecutive messages del...

Page 103: ...Requester ID Bus Number Cycle 2 Requester ID Device Function Number PM_PME PME_TO_Ack PME_Turn_off PM_Active_State_Nak 2 Cycle 1 Requester ID Bus Number Cycle 2 Requester ID Device Function Number Se...

Page 104: ...ad Configuration Transmit Message Interface The Configuration Transmit Message interface is used by the user application to transmit messages to the core The user application supplies the transmit mes...

Page 105: ...noop Latency Value cfg_msg_transmit_data 15 No Snoop Latency Requirement cfg_msg_transmit_data 14 13 Repurposing to pass PASID information assigned to s_axis_rq_tuser 180 179 inside the IP cfg_msg_tra...

Page 106: ...rol Credits This multiplexed output can be used to bring out various flow control parameters and variables related to Non Posted Header Credit maintained by the core The flow control information to br...

Page 107: ..._fc_ signals Possible values 0b VC0 1b VC1 pcie0_cfg_fc_sel pcie1_cfg_fc_sel I 3 Flow Control Informational Select These inputs select the type of flow control to bring out on the cfg_fc_ outputs of t...

Page 108: ...by the Non Posted requests it sent in the previous clock cycles if any pcie0_pcie_tfc_npd_av pcie1_pcie_tfc_npd_av O 4 This output provides an indication of the currently available payload credit for...

Page 109: ...High if it does not need to delay the return of the completions for the configuration write transactions causing power state changes pcie0_cfg_power_state_change_interrupt pcie1_cfg_power_state_change...

Page 110: ...onfiguration accesses to the physical function The core will issue CRS to configurations requests to a particular Physical Function till pcie n _cfg_flr_done is not asserted when pcie n _cfg_flr_in_pr...

Page 111: ...Legacy Interrupt Interface Port Descriptions Name I O Width Description pcie0_cfg_interrupt_int pcie1_cfg_interrupt_int I 4 Configuration INTx Vector When the core is configured as EP these four input...

Page 112: ...e same cycle The core internally registers the interrupt condition on the 0 to 1 transition of any bit in pcie n _cfg_msi_mint_vector After asserting an interrupt the user logic must wait for the pcie...

Page 113: ...ber on the pcie n _cfg_msi_pending_status_function_num input and activate the pcie n _cfg_msi_pending_status_data_enable input for one cycle The core then latches the new status in its MSI Pending Bit...

Page 114: ...face Port Descriptions Name I O Width Description pcie0_cfg_msix_enable O 4 Configuration Interrupt MSI X Function Enabled These outputs reflect the setting of the MSI X Enable bits of the MSI X Contr...

Page 115: ...SI X Data Valid The assertion of this signal by the user indicates a request from the user to send an MSI X interrupt The user must place the identifying information on the designated inputs before as...

Page 116: ...asserting an interrupt the user logic must wait for the pcie0_cfg_msix_sent or pcie0_cfg_msix_fail indication from the core before asserting a new interrupt pcie0_cfg_msix_function_number pcie1_cfg_ms...

Page 117: ..._msix_int_vector 31 0 respectively Bit i of pcie n _cfg_msix_mint_vector 31 0 represents interrupt vectori and only one of the bits of this bus can be set to 1 when asserting pcie n _cfg_msix_int_vect...

Page 118: ...f the bits of pcie n _cfg_msix_mint_vector as a query for the status of its Pending Bit The user must also place the Function number of the Pending Bit being queried on the pcie n _cfg_msix_function_n...

Page 119: ...g MSI X if it is including a TPH in the MSI or MSI X transaction pcie0_cfg_msi_tph_type pcie1_cfg_msi_tph_type I 2 Configuration Interrupt MSI MSI X TPH Type When pcie n _cfg_msi_tph_present is 1 b1 t...

Page 120: ..._ext_write_received O 1 Configuration Extend Write Received The Block asserts this output when it has received a configuration write request from the link Set when PCI Express Extended Configuration S...

Page 121: ...ects the assertions of this signal within 262144 h4_0000 clock cycles of user clock after receiving the read request on pcie n _cfg_ext_read_received signal If no response is received by this time the...

Page 122: ...m specifications The Versal ACAP CPM Mode for PCIe supports Xilinx proprietary read write configuration interfaces into this register space and supports up to four Physical Functions PFs and 252 Virtu...

Page 123: ...rface PRI Feature DLLP CCIX Transport DVSEC through configuration space extension CCIX Protocol DVSEC through configuration space extension Transaction Tag Scaling as Requester and Completer Flow Cont...

Page 124: ...ve a frequency of 62 5 125 or 250 MHz depending on the configured link speed and width The user_clk should be used to interface with the CPM With the user logic any available clocks can be used Each l...

Page 125: ...k X22724 051419 Figure 15 Open System Add In Card Using 100 MHz Reference Clock PCIe Link PCI Express Connector Device Endpoint Transceivers 100 MHz with SSC PCI Express Clock PCI Express Add In Card...

Page 126: ...leter interface in the user side interfaces associated with the 1024 bit AXI4 Stream Interface Note All signals in the waves are not appended with pcie0 or pcie1 ports but apply to both pcie0 and pcie...

Page 127: ...r 464 0 m_axis_cq_tlast m_axis_cq_tkeep 31 0 m_axis_cq_tready m_axis_cq_tvalid m_axis_cq_tdata 1023 0 The completer request interface supports two distinct data alignment modes selected during core cu...

Page 128: ...ing the 128 bit address aligned mode The descriptions in the next sections assume a single TLP per beat The operation of the interface with the straddle option enabled is described in Straddle Option...

Page 129: ...ion 127 63 0 X12217 R R BAR ID 0 1 2 3 4 5 6 7 0 0 1 2 3 4 5 6 7 1 0 1 2 3 4 5 6 7 2 0 1 2 3 4 5 6 7 3 DW 0 Address 63 2 Address Type AT 0 1 2 3 4 5 6 7 4 0 1 2 3 4 5 6 7 5 0 1 2 3 4 5 6 7 6 0 1 2 3 4...

Page 130: ...nvalid Request Invalid Completion Page Request PRG Response Figure 19 Completer Request Descriptor Format for ATS Messages 0 1 2 3 4 5 6 7 0 0 1 2 3 4 5 6 7 1 0 1 2 3 4 5 6 7 2 0 1 2 3 4 5 6 7 3 DW 0...

Page 131: ...ed 63 2 Address This field applies to memory I O and Atomic Op requests It provides the address from the TL header This is the address of the first Dword referenced by the request The First_BE bits fr...

Page 132: ...s 110 Expansion ROM Access Note In Root Port RP mode BAR ID is always 000 For 64 bit transactions the BAR number is given as the lower address of the matching pair of BARs that is 0 2 or 4 120 115 BAR...

Page 133: ...allowed only in Legacy Devices 1000 Type 0 Configuration Read Request on Requester side only 1001 Type 1 Configuration Read Request on Requester side only 1010 Type 0 Configuration Write Request on R...

Page 134: ...is_cq_tuser bus These are activated in the first beat of the packet and provides information of the valid bytes in the first and last Dwords of the payload The m_axi_cq_tuser bus also provides several...

Page 135: ...mory write when the core transfers a one Dword payload with the byte_en bits all set to 0 Thus the user logic can in all cases use the byte_en signals directly to enable the writing of the associated...

Page 136: ...he delivery of the payload always starts in the second quarter bits 255 128 of the first beat following the descriptor in the first quarter The first Dword the payload can appear on any of the four Dw...

Page 137: ...Memory Write Transaction on the Completer Request Interface 128 bit Address Aligned Mode Chapter 4 Designing with the Core PG346 v3 3 November 16 2022 www xilinx com CPM Mode for PCI Express 137 Send...

Page 138: ...s on the bus Figure 23 Memory Read Transaction on the Completer Request Interface The byte enable bits associated with the read request for the first and last Dwords are supplied by the core on the si...

Page 139: ...of Non Posted requests across the interface without affecting Posted requests The user logic signals the availability of buffers to receive Non Posted requests to the core using the pcie0_cq_np_req 1...

Page 140: ...onse Thus when the user logic has adequate buffer space available it should provide the credit in advance so that Non Posted requests are not held up by the core for lack of credit Note pcie1_cq_np_re...

Page 141: ...sponding TLP ending in this beat For TLPs with a payload the offset for the last byte can be also be determined from the starting address and length of the TLP or from the byte enable signals byte_en...

Page 142: ...thout any gaps The first request TLP REQ 1 starts at Dword position 0 of Beat 1 and ends in Dword position 5 of Beat 3 The second TLP REQ 2 starts in Dword position 8 of the same beat This second TLP...

Page 143: ...and the start of the first byte of the payload is filled with null bytes The interface also supports a straddle option that allows the transfer of up to two TLPs in the same beat across the interface...

Page 144: ...0 0 1 2 3 4 5 6 7 11 DW 2 Device Function Attr Poisoned Completion 64 32 Address 6 0 Completion Status Bus Completer ID Completer ID Enable Force ECRC R Bus Device Function Requester ID 95 63 0 Locked...

Page 145: ...se 11 bits indicate the size of the payload of the current packet in Dwords Its range is 0 1K Dwords This field must be set to 1 for I O read Completions and 0 for I O write Completions The Dword coun...

Page 146: ...e bit in the descriptor Root Port mode Downstream Port ARI enabled Bits 79 72 must be set to the Completer Function number ARI disabled Bits 74 72 must be set to the Completer Function number Bits 79...

Page 147: ...request copied from the request Bit 92 is the No Snoop bit bit 93 is the Relaxed Ordering bit and bit 94 is the ID Based Ordering bit 95 Reserved Reserved for future use Completions with Successful Co...

Page 148: ...ng Also in the case of non contiguous reads not all bytes in the data block returned are be valid In that case the user application must return the valid bytes in the proper positions with null bytes...

Page 149: ...its 128 bit quarter the offset of the first payload byte must correspond to the least significant bits of the Lower Address field setting in the corresponding descriptor The following timing diagram...

Page 150: ...le Internal Error using the Advanced Error Reporting AER mechanisms Completions with Error Status UR and CA When responding to a request received on the completer request interface with an Unsupported...

Page 151: ...ous stream with no packet boundaries Thus the signals m_axis_cc_tkeep and m_axis_cc_tlast are not useful in determining the boundaries of TLPs delivered on the interface Instead delineation of TLPs is...

Page 152: ...set only when the signals is_eop 0 and is_sop 0 are also be High in the same beat is_eop1_ptr 3 0 When is_eop 1 is asserted is_eop1_ptr 3 0 must provide the offset of the last Dword of the second TLP...

Page 153: ...Enabled 1024 bit Interface 1024 Bit Requester Interface This section describes the operation of the user side Requester interface associated with the 1024 bit AXI4 Stream Interface Chapter 4 Designing...

Page 154: ...tes the signals associated with the requester request interface of the core The core delivers each TLP on this interface as an AXI4 Stream packet The packet starts with a 128 bit descriptor followed b...

Page 155: ...Signals Integrated Block for PCIe User Application PCIe Requester Request Interface AXI4 Stream Master PCIe Requester Interface s_axis_rq_tdata 1023 0 s_axis_rq_valid s_axis_rq_tready s_axis_rq_tlast...

Page 156: ...interface of the core as an independent AXI4 Stream packet Each packet must start with a descriptor and can have payload data following the descriptor The descriptor is always 16 bytes long and must...

Page 157: ...ID Device Function 127 63 0 X12212 0 1 2 3 4 5 6 7 0 0 1 2 3 4 5 6 7 1 0 1 2 3 4 5 6 7 2 0 1 2 3 4 5 6 7 3 DW 0 Address 63 2 Address Type AT 0 1 2 3 4 5 6 7 4 0 1 2 3 4 5 6 7 5 0 1 2 3 4 5 6 7 6 0 1 2...

Page 158: ...nvalid Request Invalid Completion Page Request PRG Response Figure 33 Requester Request Descriptor Format for ATS Messages 0 1 2 3 4 5 6 7 0 0 1 2 3 4 5 6 7 1 0 1 2 3 4 5 6 7 2 0 1 2 3 4 5 6 7 3 DW 0...

Page 159: ...ress of the first Dword referenced by the request The user logic must also set the First_BE and Last_BE bits in s_axis_rq_tuser to indicate the valid bytes in the first and last Dwords respectively Wh...

Page 160: ...conjunction with Requester ID Enable bit in the descriptor 95 88 Requester Bus Number Bus number associated with the Requester Function Endpoint mode Not used Upstream Port for Switch use case Endpoi...

Page 161: ...n Device Number bits 87 83 when ARI is not enabled Note When 10 bit tags are enabled for the requester the Requester ID Enable is implicitly assumed to be set to 0 in the EP mode and set to 1 in all o...

Page 162: ...ansfer of a packet the m_axis_rq_tkeep bits can be 0 only in the last beat of the packet when the packet does not fill the entire width of the interface The requester request interface also includes t...

Page 163: ...the 128 bit address aligned mode the delivery of the payload always starts in the second 128 bit quarter of the 1024 bit word following the descriptor in the first quarter The user application must c...

Page 164: ...of the packet The core are pull down s_axis_rq_tready to prolong the beat The signal s_axis_rq_tlast must be set in the last beat of the packet and the bits in s_axis_rq_tkeep must be set in all Dwor...

Page 165: ...uest with the following changes in how the payload is aligned on the datapath In the Dword aligned mode the first Dword of the payload follows the last Dword of the descriptor with no gaps between the...

Page 166: ...the Root Complex it is attached to as an Uncorrectable Internal Error using the Advanced Error Reporting AER mechanisms Straddle Option on RQ Interface The PCIe core has the capability to start the t...

Page 167: ...op 1 can be set only when the signals is_eop 0 and is_sop 0 are also be High in the same beat is_eop1_ptr 3 0 When is_eop 1 is asserted is_eop1_ptr 3 0 must provide the offset of the last Dword of the...

Page 168: ...ransfer of Request TLPs on the Requester Request Interface with the Straddle Option Enabled Chapter 4 Designing with the Core PG346 v3 3 November 16 2022 www xilinx com CPM Mode for PCI Express 168 Se...

Page 169: ...st copy the tag so that any Completions delivered by the core in response to the request can be matched to the request In this mode logic within the core checks for the Split Completion Table full con...

Page 170: ...rently available for Non Posted requests 0000 no credit available 0001 1 credit available 0010 2 credits 1111 15 or more credits available pcie_tfc_npd_av 3 0 These outputs indicate the Data Credit cu...

Page 171: ...transmits them on the link In cases where the user logic would like to have precise control of the order of transactions sent on the requester request interface and the completer completion interface...

Page 172: ...mpletion Interface Operation 1024 bits Figure 40 Requester Completion Interface Signals Integrated Block for PCI Express User Application PCIe Requester Completion Interface AX14 Stream Slave PCIe Req...

Page 173: ...aligned mode can be used on the requester completion interface only if the requester request interface is also configured to use the 128 bit address aligned mode Requester Completion Descriptor Format...

Page 174: ...0 1 2 3 4 5 6 7 10 0 1 2 3 4 5 6 7 11 DW 2 Device Function Attr Poisoned Completion 63 32 Address 11 0 Completion Status Bus Completer ID Locked Read Completion R R Error Code Request Completed Bus D...

Page 175: ...rrespond to a Completion TLP 28 16 Byte Count These 13 bits can have values in the range of 0 4 096 bytes If a Memory Read Request is completed using a single Completion the Byte Count value indicates...

Page 176: ...47 T9 When 10 bit tags are enabled on the requester side this field provides bit 9 of the PCIe tag associated with the Completion This bit is reserved when 10 bit tags are disabled on the requester si...

Page 177: ...f Completions with Data In the Dword aligned mode the transfer starts with the three descriptor Dwords followed immediately by the payload Dwords The entire TLP consisting of the descriptor and payloa...

Page 178: ...e transfer of Completions The byte enable outputs byte_en 127 0 one per byte lane indicate the valid bytes in the payload These signals are asserted only when a valid payload byte is in the correspond...

Page 179: ...rting Dword address of the data block being transferred as conveyed in the Lower Address field of the descriptor is assumed to be m 16 1 for some integer m The size of the data block is assumed to be...

Page 180: ...rst Dword of the descriptor until the last Dword of the payload The alignment of the first Dword on the data bus within its 128 bit field is determined by the setting of the addr_offset 1 0 input of t...

Page 181: ...PCIe core has the capability to start up to four Completions in the same beat on the requester completion interface This straddle option is enabled during core customization in the Vivado IDE The str...

Page 182: ...the second TLP and is_sop2_ptr 1 0 provides the starting position of the third TLP 1111 Four new TLPs are starting in this beat is_sop0_ptr 1 0 provides the starting position of the first TLP is_sop1_...

Page 183: ...r 3 0 When is_eop 0 is set this field provides the offset of the last Dword of the first TLP ending in this beat It can take any value from 0 through 15 The offset for the last byte can be determined...

Page 184: ...d offsets of the new Completions 5 6 and 7 are provided by is_sop0_ptr is_sop1_ptr and is_sop2_ptr respectively The ending offsets of Completions 4 5 6 and 7 are indicated by is_eop0_ptr is_eop1_ptr i...

Page 185: ...sserting the discontinue signal in the m_axis_rc_tuser bus in the last beat of the packet This occurs when the core has detected an uncorrectable error while reading data from its internal memories Th...

Page 186: ...est but its Requester ID TC or Attr fields did not match with the parameters of the outstanding request The user logic should discard any data that follows the descriptor In addition if the Request Co...

Page 187: ...ic however the user logic must ensure that a tag assigned to a request is not reused until the core has signaled the termination of the request by setting the Request Completed bit in the completion d...

Page 188: ...Suite User Guide Getting Started UG910 Vivado Design Suite User Guide Logic Simulation UG900 Customizing and Generating the CIPS IP Core for CPM4 This section includes information about using the Viv...

Page 189: ...IP integrator 3 Right click on the block design canvas and from the context menu select Add IP 4 Search for cips 5 Double click the Control Interface and Processing System IP core to customize it Cha...

Page 190: ...ate options required for presets and click Next Note For information about the option presets see Control Interface and Processing System LogiCORE IP Product Guide PG352 Chapter 5 Design Flow Steps PG...

Page 191: ...7 Click the CPM block to configure the core The CPM Basic Configuration page displays Chapter 5 Design Flow Steps PG346 v3 3 November 16 2022 www xilinx com CPM Mode for PCI Express 191 Send Feedback...

Page 192: ...PCIE and select the lane width Table 52 Available Lane Width Combinations PCIe Port 0 PCIe Port 1 X1 X2 X4 or X8 X1 X2 X4 or X8 X16 Not available Note PCIe Port 1 is available only if the lane width o...

Page 193: ...t on the first page of the Customize IP dialog box Next section will explain the parameters available in each mode 11 If applicable in the Configuration Options pane expand CPM and click PCIE Controll...

Page 194: ...on should match the MIO that is connected to the PCIe reset I O in the board schematic In the figure below PMC MIO 38 is selected to correspond to PCIe reset MIO 38 b If PCIe Port 1 is enabled Next to...

Page 195: ...B IOs select them in the Peripherals section in a similar manner See the Versal ACAP Technical Reference Manual AM011 for more details on these interfaces Basic Mode Parameters The Basic mode paramete...

Page 196: ...ect the Interface Width The default interface width set in the Customize IP dialog box is the lowest possible interface width AXI ST Alignment Mode When a payload is present there are two options for...

Page 197: ...o select the number of physical functions The number of physical functions supported is 4 PFx Max Payload Size This field indicates the maximum payload size that the device or function can support for...

Page 198: ...ion bit in the Link Status register When this option is selected the link is synchronously clocked When this option is deselected asynchronous clock in SRNS mode is supported SRNS refers to a separate...

Page 199: ...d selected Setting the value to 0000h can cause compliance testing issues Class Code The Class Code identifies the general function of a device and is divided into three byte size fields Base Class Br...

Page 200: ...All BAR registers share these options Checkbox Click the checkbox to enable the BAR deselect the checkbox to disable the BAR Type Bars can either be I O or Memory I O I O BARs can only be 32 bit the P...

Page 201: ...B in size should be avoided The minimum I O space allowed is 16 bytes use of I O space should be avoided in all new designs Prefetchability is the ability of memory space to be prefetched A memory spa...

Page 202: ...nd are disabled MSI Capabilities PF0 PF1 PF2 PF3 Enable MSI Capability Structure Indicates that the MSI Capability structure exists Note Although it is possible to not enable MSI or MSI X the result w...

Page 203: ...n in the following figure includes additional settings The following parameters are visible on the Basic page when the Advanced mode is selected Figure 51 Basic Tab Advanced Mode PCIe Link Debug This...

Page 204: ...X capabilities select Advanced mode and then select the required options on the Capabilities tab There are four options to choose from MSI X External In this mode you need to implement MSI X External...

Page 205: ...able and Pending Bit Array in the application MSI X Table Settings Defines the MSI X Table structure Table Size Specifies the MSI X Table size Table Size field is expecting N 1 interrupts 0x0F will co...

Page 206: ...lable that can be flexibly used across the four physical functions Number of VFs for any enabled PF cannot be 0 PFx Dependency Link Indicates the SR IOV Functional Dependency Link for the physical fun...

Page 207: ...for PF1 is a function of how many VFs are attached to PF0 and is defined in the following pseudo code PF1_FIRST_VF_OFFSET FIRST_VF_OFFSET NUM_PF0_VFs 1 Similarly for other PFs PF2_FIRST_VF_OFFSET FIR...

Page 208: ...t BARs The address space can be as small as 16 bytes or as large as 3 gigabytes Used for memory to I O 64 bit BARs The address space can be as small as 128 bytes or as large as 256 gigabytes Used for...

Page 209: ...d address space Generally memory spaces less than 4 KB in size should be avoided The minimum I O space allowed is 16 bytes I O space should be avoided in all new designs A memory space is prefetchable...

Page 210: ...ndpoint mode and not supported in other modes it is also not supported in non synchronous clocking mode ASPM L0 is supported only on designs generated for Gen1 and Gen2 and in endpoint modes only Figu...

Page 211: ...mation about using the Vivado Design Suite to customize and generate the Control Interfaces and Processing System IP core This section configures the CIPS IP core to access the CPM PCIe controllers di...

Page 212: ...s in the IP integrator 3 Right click on the block design canvas and from the context menu select Add IP 4 Search for cips 5 Double click the Control Interface and Processing System IP core to customiz...

Page 213: ...esets see Control Interface and Processing System LogiCORE IP Product Guide PG352 7 Click the CPM block to configure the core Chapter 5 Design Flow Steps PG346 v3 3 November 16 2022 www xilinx com CPM...

Page 214: ...The CPM Basic Configuration page displays Chapter 5 Design Flow Steps PG346 v3 3 November 16 2022 www xilinx com CPM Mode for PCI Express 214 Send Feedback...

Page 215: ...PCIE and select the lane width Table 56 Available Lane Width Combinations PCIe Port 0 PCIe Port 1 X1 X2 X4 or X8 X1 X2 X4 or X8 X16 Not available Note PCIe Port 1 is available only if the lane width o...

Page 216: ...click PCIE Controller 1 Configuration to customize PCIe Port 1 12 After configuring the PCIe controller click OK to return to the Configure screen as shown below 13 Click PS PMC and click IO configura...

Page 217: ...IO 39 based on which MIO is connected to the PCIe reset I O in the board schematic 15 If the board will boot from serial NOR flash select the a QSPI or OSPI option in Boot Mode options to enable progr...

Page 218: ...Reference Manual AM011 for more details on these interfaces Basic Mode Parameters The Basic mode parameters are explained in this section Basic Tab The following figure shows the initial customization...

Page 219: ...device Higher link speed cores are capable of training to a lower link speed if connected to a lower link speed capable device Maximum Link Width The core requires the selection of the initial lane wi...

Page 220: ...and AXI ST RQ RC Frame Straddle When 512 bit AXI ST interface width is selected AXI ST frame Straddle is supported for CQ CC RQ and RC AXI ST interfaces Option to select CQ and CC AXI ST frame stradd...

Page 221: ...a Requester The options are When selected 10 bit Requester Tag field support 768 tags When deselected 8 5 bit Tag supported depending on Extended Tag Field selection Enable Slot Clock Configuration En...

Page 222: ...any value change this value for the application The default Device ID parameter is based on The device family B for Versal ACAP EP or RP mode Link width 1 for x1 2 for x2 4 for x4 8 for x8 and F for...

Page 223: ...Broadly identifies the type of function performed by the device Sub Class More specifically identifies the device function Interface Defines a specific register level programming interface if any all...

Page 224: ...R registers share these options Checkbox Click the checkbox to enable the BAR deselect the checkbox to disable the BAR Type Bars can either be I O or Memory I O I O BARs can only be 32 bit the Prefetc...

Page 225: ...B in size should be avoided The minimum I O space allowed is 16 bytes use of I O space should be avoided in all new designs Prefetchability is the ability of memory space to be prefetched A memory spa...

Page 226: ...pability structure exists Note Although it is possible to not enable MSI or MSI X the result would be a non compliant core The PCI Express Base Specification requires that MSI MSI X or both be enabled...

Page 227: ...page with Advanced mode selected shown in the following figure includes additional settings The following parameters are visible on the Basic page when the Advanced mode is selected Figure 63 Basic Ta...

Page 228: ...Capabilities Tab Advanced Mode Function Level Reset Enable Function Level Reset FLR FLR is supported when the PCIe IP is configured as Endpoint SRIOV Capabilities Enables Single Root Port I O Virtual...

Page 229: ...re available in Advanced mode only To enable MSI X capabilities select Advanced mode and then select the required options on the Capabilities page There are four options to choose from MSI X External...

Page 230: ...Address Register that points to the base of the MSI X Table BAR Indicator Indicates the Base Address Register in the Configuration Space used to map the function in the MSI X Table onto memory space F...

Page 231: ...k for the physical function The programming model for a device can have vendor specific dependencies between sets of functions The Function Dependency Link field is used to describe these dependencies...

Page 232: ...OFFSET FIRST_VF_OFFSET NUM_PF0_VFs 1 Similarly for other PFs PF2_FIRST_VF_OFFSET FIRST_VF_OFFSET NUM_PF0_VFs NUM_PF1_VFs 2 PF3_FIRST_VF_OFFSET FIRST_VF_OFFSET NUM_PF0_VFs NUM_PF1_VFs NUM_PF2_VFs 3 VF...

Page 233: ...32 bit BARs or one 64 bit BAR SR IOV BARs can be one of two sizes 32 bit BARs The address space can be as small as 16 bytes or as large as 3 gigabytes Used for memory to I O 64 bit BARs The address sp...

Page 234: ...register Memory or I O settings indicate whether the address space is defined as memory or I O The base address register only responds to commands that access the specified address space Generally mem...

Page 235: ...ced Options tab also enables you to choose ECRC check in AER Capability ARI DSN Virtual Channel MCAP ATS PRI PASID and PCI Express Extended Config space and PCI Legacy Extended space Figure 68 Adv Opt...

Page 236: ...ters tab enables you to enable disable interfaces that are not required for your application Figure 69 Interface Parameters Tab Chapter 5 Design Flow Steps PG346 v3 3 November 16 2022 www xilinx com C...

Page 237: ...x16 requires four adjacent GT Quads that are bonded and are in the same SLR PL PCIe blocks should use GTs adjacent to the PCIe block where possible CPM has a fixed connectivity to GTs based on the CP...

Page 238: ...QUAD 1 0 When we apply lane_reversal true then PIPE signals of the PCIe MAC 1 0 connects to PIPE signals of the GT QUAD 0 1 When we apply lane_order Top then PIPE signals of the PCIe MAC 1 0 connects...

Page 239: ...rom CPM This corresponds to the same location as PCIe lane 8 for a x16 link configuration The fourth GT Quad in this configuration is not use by CPM and can be used to implement PL GT based solutions...

Page 240: ...his configuration CPM4 Additional Considerations To facilitate migration from UltraScale or UltraScale designs boards may be designed to use either CPM4 or PL PCIe integrated blocks to implement PCIe...

Page 241: ...l apply and the additional PCIe reset output pins will be exposed at the boundary of the CIPS IP If the CPM4 PCIe controller is enabled the PCIe reset is used internal to the CPM4 and is not routed to...

Page 242: ...02 All CPM Controller 1 N A GTY_QUAD_X0Y3 GTY_QUAD_X0Y2 GTY_QUAD_X0Y2 CPM Controller 0 GTY_QUAD_X0Y3 GTY_QUAD_X0Y2 GTY_QUAD_X0Y1 GTY_QUAD_X0Y0 GTY_QUAD_X0Y1 GTY_QUAD_X0Y0 GTY_QUAD_X0Y0 XCVC1902 XCVM15...

Page 243: ...in card designs the reference clock is sourced from the edge connector In other cases such as system board designs embedded designs and cabled interconnect a local oscillator is typically required RE...

Page 244: ...will require the guidance in this section 3 Guidance for CPM5 Migration from Specifically Identified Engineering Sample Devices Designers intending to migrate their design containing CPM5 from specifi...

Page 245: ...ad 104 REFCLK 0 x8 x4 Not Required x8 x8 x8 x8 Controller 1 0 7 Controller 0 0 7 Quad 104 REFCLK 0 Quad 105 REFCLK 01 Quad 102 REFCLK 0 Quad 103 REFCLK 01 x8 x4 x4 x8 x4 x4 Not Required x8 x8 Controll...

Page 246: ...equired for 16 GT sec lane data rate or lower 2 A x1 link width uses lane 0 of the x4 configuration A x2 link width uses lanes 1 0 of the x4 configuration This should be reversed on the PCB Board desi...

Page 247: ...ering above typically results in lanes crossing for x4 and x2 endpoint configurations In this scenario Xilinx recommends physically reversing the lanes in the PCB design board traces This will typical...

Page 248: ...1502 VSVA2785 ES1 VP1502 VSVA3340 ES1 VP1552 VSVA2785 ES1 VP1702 VSVA3340 ES1 VP1802 LSVC4072 ES1 Versal HBM VH1522 VSVA3697 ES1 VH1542 VSVA3697 ES1 VH1582 VSVA3697 ES1 Appendix B GT Selection and Pin...

Page 249: ...4 Controller 1 3 0 Controller 0 3 0 Quad 104 Refclk 0 Quad 102 Refclk 0 On PCB x4 x4 Controller 1 3 0 Quad 104 Refclk 0 On PCB x4 x4 Controller 0 3 0 Quad 102 Refclk 0 On PCB x4 x8 x4 x8 Controller 1...

Page 250: ...allowed GTYP quad placements and lane ordering the PCB designer might conclude it is not feasible to meet length loss or other signaling requirements while physically implementing lane reversal on th...

Page 251: ...ded placement tables For additional migration support contact your Xilinx representative RESET Considerations RESET placement options do not change CPM5 Configuration Considerations Design migration r...

Page 252: ...2 XCVH1522 XCVH1542 XCVH1582 XCVH1782 All CPM Controller 1 N A GTY_QUAD_X0Y5 GTY_QUAD_X0Y4 GTY_QUAD_X0Y4 CPM Controller 0 GTY_QUAD_X0Y5 GTY_QUAD_X0Y4 GTY_QUAD_X0Y3 GTY_QUAD_X0Y2 GTY_QUAD_X0Y3 GTY_QUAD...

Page 253: ...gn process can be found on the Xilinx Support web page or by using the Xilinx Documentation Navigator Download the Xilinx Documentation Navigator from the Downloads page For more information about thi...

Page 254: ...core that will be recognized by the Vivado Hardware Manager and provide PCIe specific debug information and view The debug view provides information relating to the current link speed current link wi...

Page 255: ...Versal designs This is also detailed in the description below 2 Add the Debug Hub IP to the design and use the following configuration options to enable the Debug Hub AXI Memory Mapped interface along...

Page 256: ...PMC PL PS Interfaces and enable at least one PL reset in Number of PL Resets and the M_AXI_LPD AXI master Appendix C Debugging PG346 v3 3 November 16 2022 www xilinx com CPM Mode for PCI Express 256 S...

Page 257: ...4 Add and configure the Processor System Reset IP Appendix C Debugging PG346 v3 3 November 16 2022 www xilinx com CPM Mode for PCI Express 257 Send Feedback...

Page 258: ...Ps as shown in the following figures This may need to be customized to fit with existing design connectivity Appendix C Debugging PG346 v3 3 November 16 2022 www xilinx com CPM Mode for PCI Express 25...

Page 259: ...do Hardware Manager to the FPGA device and associated PCIe Link Debug enabled design 1 Open the Hardware Manager 2 Select the device from the Tools Program Device drop down menu 3 Select the pdi and l...

Page 260: ...n the final or current LTSSM state is shown in yellow and the number of times each transition was traversed is identified on the arcs between states In addition to the graphical display the report_hw_...

Page 261: ...not perform debug until the FPGA is already loaded with a FPGA hardware design that implements HSDP over PCIe and PCIe link to the host PC is established This is achieved by loading an HSDP over PCIe...

Page 262: ...mponent when performing debug over PCIe Figure 71 HSDP over PCIe Hardware and Software Components Host PC HSDP PCIe Driver The HSDP PCIe driver provides connectivity to the debug over PCIe enabled FPG...

Page 263: ...here are two distinct methods to exercise the HSDP over PCIe feature such as mgmt mode and user mode Each of these methods has its own design requirements and supporting driver code User Mode The user...

Page 264: ...nates responses to the Host PC The HSDP DMA block must be accessible for setup from a PCIe BAR through CPM s AXI Master Bridge at base address 0xFE5F0000 The physical address is fixed and cannot be re...

Page 265: ...r must have the debug hub slave mapped to its address space and the CPM master must have the CPM slave mapped to its address space For CPM4 you can configure up to 6 AXI BARs each with address transla...

Page 266: ...ddress Map for HSDP over PCIe Management Mode Debug for CPM4 Figure 77 AXI BARs for HSDP over PCIe Management Mode Debug for CPM4 Appendix D Using the High Speed Debug Port Over PCIe for Design Debug...

Page 267: ...ranslation between CPM4 and CPM5 differ significantly For CPM5 the concept of the BDF table was introduced which allows for significantly more granularity for address translation within each AXI BAR e...

Page 268: ...n and Generating a Bitstream A set of example designs are hosted on GitHub in the XilinxCEDStore repository and displayed through Vivado which can be refreshed with a valid internet connection includi...

Page 269: ...arted to allow the PCIe link to enumerate After the system is up and running you can use the Linux lspci utility to list the details for the FPGA based PCIe device Compiling and Loading the Driver The...

Page 270: ...n the configuration header file hw_server e set pcie debug hub dev hsdp_user_ BB DD F _ name Connecting the Vivado IDE to the hw_server Application for Debug Over PCIe At this point the FPGA design ha...

Page 271: ...then click through to Finish 6 The target device should be in the Hardware window and a probes file can now be specified in the Hardware Device Properties window after opening the hardware target and...

Page 272: ...ing user mode for debug 7 If using mgmt mode for debug a user can connect to the debug host PC through the XSDB application and issue direct AXI reads and writes through the PMC Appendix D Using the H...

Page 273: ...t any valid EP address be used except ECAM space in the pre read before initiating PM D3 sequence In all other cases waiting approximately 20 msec after the link rate and before attempting any PCIe ac...

Page 274: ...orrectable errors being reported on the link by both link partners i e replay timer timeout replay timer rollover receiver error 2 A PCIe Endpoint device might also log errors when Configuration PM D3...

Page 275: ...0 O Per function state of Device Control2 Register 10 Bit Tag Requester Enable bit pcie0_cfg_atomic_requester_enable 3 0 O Per function state of Device Control2 Register AtomicOp Requester Enable bit...

Page 276: ...I pcie0_s_axis_cq_tuser 228 0 O pcie0_rq_tag0 9 0 O pcie0_rq_tag1 9 0 O Ports Not Available The following table lists the ports which were deprecated in the Versal CPM4 Controllers relative to the Ult...

Page 277: ...part of the register table cfg_bus_number I Now part of the register table cfg_dpa_substate_change O Not available cfg_obff_enable O Not available phy_rdy_out O Not available sys_reset I Reset now rou...

Page 278: ...on When enabled management of up to 768 tags is possible compared to max of 256 tags in UltraScale devices Feature DLLP Data Link Feature Extended Capability structure has been added for link speed of...

Page 279: ...Design There is no example design support for this release There was a core clock frequency selection available in UltraScale for some of the configurations which is not available in Versal CPM4 Lega...

Page 280: ...otiation_pending O VC1 Resource Status Register VC Negotiation Pending bit pcie0_cfg_pasid_enable 3 0 O Per Function PASID Enable pcie0_cfg_pasid_exec_permission_enable 3 0 O Per Function PASID Exec P...

Page 281: ...or PCIe IP Table 73 Deprecated Ports Name I O Notes cfg_pm_aspm_l1_entry_reject I Now part of the register table cfg_pm_aspm_tx_l0s_entry_disable I Now part of the register table cfg_config_space_enab...

Page 282: ...fg_obff_enable O Not available phy_rdy_out O Not available sys_reset I Reset now routed via PS GT Locations CPM has a fixed connectivity to GTs based on the CPM configuration You cannot change the GT...

Page 283: ...Support Lane Margining Lane margining at the receiver extended capability structure is added for link speed of 16 0 GT s and 32 0 GT s Physical Layer 16 0 GT s Extended Capability Physical Layer 16 0...

Page 284: ...Features There used to be a core clock frequency selection available in UltraScale for some of the configurations which is not available in Versal CPM5 Legacy interrupts cannot be supported when PASID...

Page 285: ...Xilinx Design Tools DocNav At the Linux command prompt enter docnav Xilinx Design Hubs provide links to documentation organized by design tasks and other topics which you can use to learn key concept...

Page 286: ...te User Guide Designing with IP UG896 13 Versal ACAP System Software Developers Guide UG1304 14 Versal Architecture and Product Data Sheet Overview DS950 Revision History The following table shows the...

Page 287: ...lease N A Please Read Important Legal Notices The information disclosed to you hereunder the Materials is provided solely for the selection and use of Xilinx products To the maximum extent permitted b...

Page 288: ...referred to herein AUTOMOTIVE APPLICATIONS DISCLAIMER AUTOMOTIVE PRODUCTS IDENTIFIED AS XA IN THE PART NUMBER ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFF...

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