• Simultaneous assertion of
pcie_rq_tag_vld0
and
pcie_rq_tag_vld1
in the same cycle
indicates that the core has placed two allocated tags, the first on and the second on . The tag
on corresponds to an earlier request sent by the user logic and the tag on corresponds to a
later request.
•
pcie_rq_tag_vld1
is never asserted when
pcie_rq_tag_vld0
is not asserted. That is,
when there is only one tag to communicate in any cycle, it is always communicated on .
• When straddle is not in use, only a single tag can be communicated in any cycle, and
pcie_rq_tag_vld1
is never asserted.
There can be a delay of several cycles between the transfer of the request on the
s_axis_rq_tdata
bus and the assertion of
pcie_rq_tag_vld
by the core to provide the
allocated tag for the request. The user logic are, meanwhile, continue to send new requests. The
tags for requests are communicated on the
pcie_rq_tag
bus in FIFO order, so it is easy for the
user logic to associate the tag value with the request it transferred.
Avoiding Head-of-Line Blocking for Posted Requests
The core holds a Non-Posted request received on its requester request interface for lack of
transmit credit or lack of available tags. This could potentially result in HOL blocking for Posted
transactions. Such a condition can be prevented if the user logic has the ability to check the
availability of transmit credit and tags for Non-Posted transactions. The core provides the
following signals for this purpose:
•
pcie_tfc_nph_av[3:0]
: These outputs indicate the Header Credit currently available for
Non-Posted requests (0000 = no credit available, 0001 = 1 credit available, 0010 = 2 credits,
…, 1111 = 15 or more credits available).
•
pcie_tfc_npd_av[3:0]
: These outputs indicate the Data Credit currently available for
Non-Posted requests (0000 = no credit available, 0001 = 1 credit available, 0010 = 2 credits,
…, 1111 = 15 or more credits available).
•
pcie_rq_tag_av[3:0]
: These outputs indicate the number of free tags currently available
for allocation to Non-Posted requests (0000 = no tags available, 0001 = 1 tag available, 0010
= 2 tags available, …, 1111 = 15 or more tags available).
The user logic are optionally check these outputs before transmitting Non-Posted requests.
Because of internal pipeline delays, the information on these outputs is delayed by two user
clock cycles from the cycle in which the last byte of the descriptor is transferred on the requester
request interface, so the user logic must adjust these values taking into account any Non-Posted
requests transmitted in the two previous clock cycles. The following figure illustrates the
operation of these signals. In this example, the core initially had 7 Non-Posted Header Credits
and 3 Non-Posted Data Credits, and had 5 free tags available for allocation. Request 1 from the
user logic had a one-Dword payload, and therefore consumed 1 header and data credit each, and
also one tag. Requests 2 and 3 (straddled) in the next clock cycle 3 consumed 1 header credit
each, but no data credit. When the user logic presents Request 4 in clock cycle 4, it must adjust
the available credit and available tag count by taking into account Requests 1, 2 and 3, presented
Chapter 4: Designing with the Core
PG346 (v3.3) November 16, 2022
CPM Mode for PCI Express
170
