Completion is unable to pass it, the core asserts
pcie_rq_seq_num_vld0
for one cycle and
provides the sequence number of the Posted request on the
pcie_rq_seq_num0[7:0]
output. If there is a second Posted request in the pipeline in the same cycle, the core also asserts
pcie_rq_seq_num_vld1
in the same cycle and provides the sequence number of the second
Posted request on the
pcie_rq_seq_num1[7:0]
output. The user logic must therefore
monitor both sets of the sequence number outputs to check if a specific TLP has reached the
pipeline stage. Any Completions transmitted by the core after the sequence number has
appeared on
pcie_rq_seq_num0[7:0]
or
pcie_rq_seq_num1[7:0]
is guaranteed not to
pass the corresponding Posted request in the internal transmit pipeline of the core.
Requester Completion Interface Operation (1024-bits)
Figure 40: Requester Completion Interface Signals
Integrated Block for PCI Express
User Application
PCIe Requester
Completion
Interface
AX14-Stream
Slave
PCIe Requester
Interface
m_axis_rc_tdata[1023:0]
m_axis_rc_tready
m_axis_rc_tkeep[31:0]
m_axis_rc_tlast
byte_en[127:0]
is_sop0_ptr[2:0]
is_eop[7:0]
m_asix_rc_tuser[336:0]
AX14-Stream
Master
discontinue
m_axis_rc_tvalid
is_sop[7:0]
is_sop1_ptr[2:0]
is_sop2_ptr[2:0]
is_sop3_ptr[2:0]
is_eop0_ptr[4:0]
is_eop1_ptr[4:0]
is_eop2_ptr[4:0]
is_eop3_ptr[4:0]
parity[127:0]
X16714-052522
The previous figure illustrates the signals associated with the requester completion interface of
the core. When straddle is not enabled, the core delivers each TLP on this interface as an AXI4-
Stream packet. The packet starts with a 96-bit descriptor, followed by data in the case of
Completions with a payload.
Chapter 4: Designing with the Core
PG346 (v3.3) November 16, 2022
CPM Mode for PCI Express
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