Figure 35: Memory Write Transaction on the Requester Request Interface (Dword-
Aligned Mode)
The following figure illustrates the 128-bit address aligned transfer of a memory write request
from the user application across the requester request interface. For the purpose of illustration,
the starting Dword offset of the data block is assumed to be (m*16 +3), for some integer m > 0.
Its size is assumed to be n Dwords, for some
n = k*16 -1, k > 1
. In the 128-bit address-aligned
mode, the delivery of the payload always starts in the second 128-bit quarter of the 1024-bit
word, following the descriptor in the first quarter. The user application must communicate the
offset of the first Dword of the payload in the
addr_offset[15:0]
field of the
s_axis_rq_tuser
bus. The user application must also set the bits in
first_be[15:0]
to
indicate the valid bytes in the first Dword and the bits in
last_be[15:0]
to indicate the valid
bytes in the last Dword of the payload.
Chapter 4: Designing with the Core
PG346 (v3.3) November 16, 2022
CPM Mode for PCI Express
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