Xilinx Versal ACAP CPM4, Product Manual

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Figure 25: Completer Completion Descriptor Format
R
0 1 2 3 4 5 6 7
+0
0 1 2 3 4 5 6 7
+1
0 1 2 3 4 5 6 7
+2
0 1 2 3 4 5 6 7
+3
DW + 0
Byte Count Dword Count
0 1 2 3 4 5 6 7
+4
0 1 2 3 4 5 6 7
+5
0 1 2 3 4 5 6 7
+6
0 1 2 3 4 5 6 7
+7
DW + 1
Tag TC
0 1 2 3 4 5 6 7
+8
0 1 2 3 4 5 6 7
+9
0 1 2 3 4 5 6 7
+10
0 1 2 3 4 5 6 7
+11
DW + 2
Device/Function Attr
Poisoned Completion
64
32
Address [6:0]
Completion Status
Bus
Completer ID
Completer ID Enable
Force ECRC
R Bus Device/Function
Requester ID
95
63
0
Locked Read
Completion
R R AT
X12215-041619
0 1 2 3 4 5 6 7
+0
0 1 2 3 4 5 6 7
+1
0 1 2 3 4 5 6 7
+2
0 1 2 3 4 5 6 7
+3
DW + 0
Byte Count Dword Count
0 1 2 3 4 5 6 7
+4
0 1 2 3 4 5 6 7
+5
0 1 2 3 4 5 6 7
+6
0 1 2 3 4 5 6 7
+7
DW + 1
Tag TC
0 1 2 3 4 5 6 7
+8
0 1 2 3 4 5 6 7
+9
0 1 2 3 4 5 6 7
+10
0 1 2 3 4 5 6 7
+11
DW + 2
Device/Function Attr
Poisoned Completion
64
32
Address [6:0]
Completion Status
Bus
Completer ID
Completer ID Enable
Force ECRC
R Bus Device/Function
Requester ID
95
63
0
Locked Read
Completion
T9 R AT
R T8
X25572-071721
Table 49: Completer Completion Descriptor Fields
Bit Index Field Name Description
6:0 Lower Address
For memory read Completions, this field must be set to the least
significant 7 bits of the starting byte-level address of the memory
block being transferred. For all other Completions, the Lower
Address must be set to all zeros.
9:8 Address Type
This field is defined for Completions of memory transactions and
Atomic Operations only. For these Completions, the user logic must
copy the AT bits from the corresponding request descriptor into this
field. This field must be set to 0 for all other Completions.
Chapter 4: Designing with the Core
PG346 (v3.3) November 16, 2022 www.xilinx.com
CPM Mode for PCI Express 144
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