Xilinx Versal ACAP CPM4, Product Manual

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Figure 41: Requester Completion Descriptor Format
0 1 2 3 4 5 6 7
+0
0 1 2 3 4 5 6 7
+1
0 1 2 3 4 5 6 7
+2
0 1 2 3 4 5 6 7
+3
DW + 0
Byte Count Dword count
0 1 2 3 4 5 6 7
+4
0 1 2 3 4 5 6 7
+5
0 1 2 3 4 5 6 7
+6
0 1 2 3 4 5 6 7
+7
DW + 1
Tag TC
0 1 2 3 4 5 6 7
+8
0 1 2 3 4 5 6 7
+9
0 1 2 3 4 5 6 7
+10
0 1 2 3 4 5 6 7
+11
DW + 2
Device /Function Attr
Poisoned Completion
63 32
Address [11:0]
Completion Status
Bus
Completer ID
Locked Read Completion
R R
Error Code Request Completed
Bus Device /Function
Requester ID
R
0
64
95
R
X16715-030217
0 1 2 3 4 5 6 7
+0
0 1 2 3 4 5 6 7
+1
0 1 2 3 4 5 6 7
+2
0 1 2 3 4 5 6 7
+3
DW + 0
Byte Count Dword count
0 1 2 3 4 5 6 7
+4
0 1 2 3 4 5 6 7
+5
0 1 2 3 4 5 6 7
+6
0 1 2 3 4 5 6 7
+7
DW + 1
Tag TC
0 1 2 3 4 5 6 7
+8
0 1 2 3 4 5 6 7
+9
0 1 2 3 4 5 6 7
+10
0 1 2 3 4 5 6 7
+11
DW + 2
Device /Function Attr
Poisoned Completion
63 32
Address [11:0]
Completion Status
Bus
Completer ID
Locked Read Completion
R R
Error Code
Request Completed
Bus Device /Function
Requester ID
T9
0
64
95
T8
X25574-071821
Table 51: Requester Completion Descriptor Fields
Bit Index Field Name Description
11:0 Lower Address
This field provides the 12 least significant bits of the first byte
referenced by the request. The core returns this address from its
Split Completion Table, where it stores the address and other
parameters of all pending Non-Posted requests on the requester
side.
When the Completion delivered has an error, only bits [6:0] of the
address should be considered valid.
This is a byte-level address.
For ATS translation requests, this field is reserved and implied to be
zero.
Chapter 4: Designing with the Core
PG346 (v3.3) November 16, 2022 www.xilinx.com
CPM Mode for PCI Express 174
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