Xilinx Versal ACAP CPM4, Product Manual

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Table 6: Completer Request Interface Port Descriptions (cont'd)
Port I/O Width Description
pcie0_cq_np_req_count
pcie1_cq_np_req_count
O 6
This output provides the current value of the credit count
maintained by the core for delivery of Non-Posted
requests to the user logic. The core delivers a Non-Posted
request across the completer request interface only when
this credit count is non-zero. This counter saturates at a
maximum limit of 32.
Because of internal pipeline delays, there can be several
cycles of delay between the user application providing
credit on the pcie(n)_cq_np_req[1:0] inputs and the PCIe
core updating the pcie_cq_np_req_count output in
response.
This count resets on user_reset and deassertion of
user_lnk_up.
When PASID_CAP_ON is enabled then
pcie(n)_m_axis_cq_tuser [107:85]
pins are
shared with
cfg*
ports. The following table provides more information.
Table 7: Sideband Signal Descriptions in pcie(n)_m_axis_cq_tuser
Bit Index Name Width Description
3:0 first_be[3:0] 4
Byte enables for the first Dword of the payload.
This field reflects the setting of the First_BE bits in the
Transaction-Layer header of the TLP. For Memory Reads and
I/O Reads, these four bits indicate the valid bytes to be read
in the first Dword. For Memory Writes and I/O Writes, these
bits indicate the valid bytes in the first Dword of the
payload. For Atomic Operations and Messages with a
payload, these bits are set to all 1s.
This field is valid in the first beat of a packet, that is, when
sop and pcie(n)_m_axis_cq_tvalid are both High.
7:4 last_be[3:0] 4
Byte enables for the last Dword.
This field reflects the setting of the Last_BE bits in the
Transaction-Layer header of the TLP. For Memory Reads,
these four bits indicate the valid bytes to be read in the last
Dword of the block of data. For Memory Writes, these bits
indicate the valid bytes in the ending Dword of the payload.
For Atomic Operations and Messages with a payload, these
bits are set to all 1s. For Memory Reads and Writes of one
DW transfers and zero length transfers, these bits should be
0s.
This field is valid in the first beat of a packet, that is, when
sop and pcie(n)_m_axis_cq_tvalid are both High.
Chapter 3: Product Specification
PG346 (v3.3) November 16, 2022 www.xilinx.com
CPM Mode for PCI Express 43
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