Table 12: Requester Completion Interface Port Descriptions
Port
I/O
Width
Description
pcie0_m_axis_rc_tdata
pcie1_m_axis_rc_tdata
O
DW
Requester Completion Data bus.
Transmit data from the core requester completion interface
to the user application. Only the lower 128 bits are used
when the interface width is 128 bits, and only the lower 64
bits are used when the interface width is 64 bits.
Bits [255:128] are set permanently to 0 by the core when the
interface width is configured as 128 bits, and bits [255:64]
are set permanently to 0 when the interface width is
configured as 64 bits.
pcie0_m_axis_rc_tuser
pcie1_m_axis_rc_tuser
O
75
Requester Completion User Data.
This set of signals contains sideband information for the TLP
being transferred. These signals are valid when
pcie(n)_m_axis_rc_tvalid is High.
The following table describes the individual signals in this
set.
pcie0_m_axis_rc_tlast
pcie1_m_axis_rc_tlast
O
1
TLAST indication for Requester Completion Data.
The core asserts this signal in the last beat of a packet to
indicate the end of the packet. When a TLP is transferred in
a single beat, the core sets this bit in the first beat of the
transfer. This output is used only when the straddle option
is disabled. When the straddle option is enabled (for the
256-bit interface), the core sets this output permanently to
0.
pcie0_m_axis_rc_tkeep
pcie1_m_axis_rc_tkeep
O
DW/32
TKEEP indication for Requester Completion Data.
The assertion of bit i of this bus during a transfer indicates
that Dword i of the pcie(n)_m_axis_rc_tdata bus contains
valid data. The core sets this bit to 1 contiguously for all
Dwords starting from the first Dword of the descriptor to
the last Dword of the payload. Thus, pcie(n)_m_axis_rc_tkeep
sets to 1s in all beats of a packet, except in the final beat
when the total size of the packet is not a multiple of the
width of the data bus (both in Dwords). This is true for both
Dword-aligned and address-aligned modes of payload
transfer.
Bits [7:4] of this bus are set permanently to 0 by the core
when the interface width is configured as 128 bits, and bits
[7:2] are set permanently to 0 when the interface width is
configured as 64 bits.
These outputs are permanently set to all 1s when the
interface width is 256 bits and the straddle option is
enabled. The user logic must use the signals in
pcie(n)_m_axis_rc_tuser
in that case to determine the
start and end of Completion TLPs transferred over the
interface.
pcie0_m_axis_rc_tvalid
pcie1_m_axis_rc_tvalid
O
1
Requester Completion Data Valid.
The core asserts this output whenever it is driving valid data
on the pcie(n)_m_axis_rc_tdata bus. The core keeps the valid
signal asserted during the transfer of a packet. The user
application can pace the data transfer using the
pcie(n)_m_axis_rc_tready signal.
Chapter 3: Product Specification
PG346 (v3.3) November 16, 2022
CPM Mode for PCI Express
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