Table 18: Requester Request Interface Port Descriptions (512-bit Interface) (cont'd)
Name
Width
I/O
Description
pcie0_rq_tag0
pcie1_rq_tag0
8
O
When tag management for Non-Posted requests is
performed by the core (Enable Client Tag is unchecked in
the IP customization GUI), this output is used by the core to
communicate the allocated tag for each Non-Posted request
received from the client. The tag value on pcie(n)_rq_tag0 is
valid for one cycle when pcie(n)_rq_tag_vld0 is High. The
client must copy this tag and use it to associate the
completion data with the pending request.
There can be a delay of several cycles between the transfer
of the request on the pcie(n)_s_axis_rq_tdata bus and the
assertion of pcie(n)_rq_tag_vld0 by the core to provide the
allocated tag for the request. The client can, meanwhile,
continue to send new requests. The tags for requests are
communicated on this bus in FIFO order. Therefore, the
user application must associate the allocated tags with the
requests in the order in which the requests were transferred
over the interface.
When pcie(n)_rq_tag0 and pcie(n)_rq_tag1 are both valid in
the same cycle, the value on pcie(n)_rq_tag0 corresponds to
the earlier of the two requests transferred over the
interface.
pcie0_rq_tag1
pcie1_rq_tag1
8
O
The description of this signal is the same as pcie(n)_rq_tag0,
except the tag value on pcie(n)_rq_tag1 is valid for one cycle
when pcie(n)_rq_tag_vld1 is asserted.
pcie0_rq_seq_num0
pcie1_rq_seq_num0
6
O
The user may optionally use this output to keep track of the
progress of the request in the core's transmit pipeline. To
use this feature, the user application must provide a
sequence number for each request on the
pcie(n)_s_axis_rq_seq_num0[5:0] bus. The core outputs this
sequence number on the pcie(n)_rq_seq_num0[5:0] output
when the request TLP has progressed to a point in the
pipeline where a Completion TLP from the client will not be
able to pass it. This mechanism enables the client to
maintain ordering between Completions sent to the
completer completion interface of the core and Posted
requests sent to the requester request interface.
Data on the pcie(n)_rq_seq_num0[5:0] output is valid when
pcie(n)_rq_seq_num_ vld0 is High.
pcie0_rq_seq_num1
pcie1_rq_seq_num1
6
O
This output is identical in function to that of
pcie(n)_rq_seq_num0. It is used to provide a second
sequence number in the same cycle when a first sequence
number is being presented on pcie(n)_rq_seq_num0.
Data on the pcie(n)_rq_seq_num1[5:0] output is valid when
pcie(n)_rq_seq_num_ vld1 is High.
pcie0_rq_seq_num_vld0
pcie1_rq_seq_num_vld0
1
O
This output is asserted by the core for one cycle when it has
placed valid data on pcie(n)_rq_seq_num0[5:0].
pcie0_rq_seq_num_vld1
pcie1_rq_seq_num_vld1
1
O
This output is asserted by the core for one cycle when it has
placed valid data on pcie(n)_rq_seq_num1[5:0].
When PASID_CAP_ON is enabled then
pcie(n)_s_axis_rq_tuser [182:137]
pins are
shared with
cfg*
ports. The following tables provides more details.
Chapter 3: Product Specification
PG346 (v3.3) November 16, 2022
CPM Mode for PCI Express
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