Table 39: Configuration Control Interface Port Descriptions (cont'd)
Port
I/O
Width
Description
pcie0_cfg_vf_flr_in_process
pcie1_cfg_vf_flr_in_process
O
252
Function Level Reset In Process for Virtual Function
The core asserts bit i of this bus when the host initiates
a reset of virtual function i though its FLR bit in the
configuration space. The core continues to hold the
output High until the user sets the
pcie(n)_cfg_vf_flr_done input and drives
pcie(n)_cfg_vf_flr_func_num with the corresponding
function to indicate the completion of the reset
operation.
Configuration Interrupt Controller Interface
The Configuration Interrupt Controller interface allows the user application to set Legacy PCIe
interrupts, MSI interrupts, or MSI-X interrupts. The core provides the interrupt status on the
configuration interrupt sent and fail signals. The following tables define the interface ports
associated with the Configuration Interrupt Controller interface of the core.
Note: The
pcie0*
signals map to PCIe Controller 0 and
pcie1*
signals map to PCIe Controller 1 in the
port descriptions below.
Legacy Interrupt Interface
Table 40: Legacy Interrupt Interface Port Descriptions
Name
I/O
Width
Description
pcie0_cfg_interrupt_int
pcie1_cfg_interrupt_int
I
4
Configuration INTx Vector: When the core is configured
as EP, these four inputs are used by the user application
to signal an interrupt from any of its PCI Functions to the
RC using the Legacy PCI Express Interrupt Delivery
mechanism of PCI Express. These four inputs correspond
to INTA, INTB, INTC, and INTD of the PCI bus, respectively.
Asserting one of these signals causes the core to send out
an Assert_INTx message, and deasserting the signal
causes the core to transmit a Deassert_INTx message.
pcie0_cfg_interrupt_sent
pcie1_cfg_interrupt_sent
O
1
Configuration INTx Sent: A pulse on this output indicates
that the core has sent an INTx Assert or Deassert
message in response to a change in the state of one of
the pcie(n)_cfg_interrupt_int inputs.
pcie0_cfg_interrupt_pending
pcie1_cfg_interrupt_pending
I
4
Configuration INTx Interrupt Pending: Per Function
indication of a pending interrupt from the user.
pcie(n)_cfg_interrupt_pending[0] corresponds to Function
#0. Each of these inputs is connected to the Interrupt
Pending bits of the PCI Status Register of the
corresponding Function.
Chapter 3: Product Specification
PG346 (v3.3) November 16, 2022
CPM Mode for PCI Express
111
