Configuration Received Message Interface
The Configuration Received Message interface indicates to the logic that a decodable message
from the link, the parameters associated with the data, and the type of message have been
received. The following table defines the ports in the Configuration Received Message interface
of the core.
Note: Configuration Received Message interface is available only for PCIe Controller 0.
Table 33: Configuration Received Message Interface
Port
I/O
Width
Description
pcie0_cfg_msg_received
O
1
Configuration Received a Decodable Message.
The core asserts this output for one or more consecutive
clock cycles when it has received a decodable message
from the link. The duration of its assertion is determined
by the type of message. The core transfers any
parameters associated with the message on the
pcie0_cfg_msg_data[7:0]output in one or more cycles
when pcie0_cfg_msg_received is High. The following table
lists the number of cycles of pcie0_cfg_msg_received
assertion, and the parameters transferred on
cfg_msg_data[7:0] in each cycle, for each type of
message.
The core inserts at least a one-cycle gap between two
consecutive messages delivered on this interface when
the pcie0_cfg_msg_received interface is enabled.
The Configuration Received Message interface must be
enabled during core configuration in the Vivado IDE.
pcie0_cfg_msg_received_data
O
8
This bus is used to transfer any parameters associated
with the Received Message. The information it carries in
each cycle for various message types is listed in the
previous table.
pcie0_cfg_msg_received_type
O
5
Received message type.
When pcie0_cfg_msg_received is High, these five bits
indicate the type of message being signaled by the core.
The various message types are listed in the previous
table.
Table 34: Message Type Encoding on Receive Message Interface
cfg_msg_received_type[4:0]
Message Type
0
ERR_COR
1
ERR_NONFATAL
2
ERR_FATAL
3
Assert_INTA
4
Deassert_ INTA
5
Assert_INTB
6
Deassert_ INTB
7
Assert_INTC
8
Deassert_ INTC
Chapter 3: Product Specification
PG346 (v3.3) November 16, 2022
CPM Mode for PCI Express
102
