Table 32: Configuration Status Interface Port Descriptions (cont'd)
Port
I/O
Width
Description
pcie0_cfg_local_error_valid
pcie1_cfg_local_error_valid
O
1
Local Error Conditions Valid: Block activates this output
for one cycle when any of the errors in
cfg_local_error_out[4:0] are encountered. When driven 1b
cfg_local_error_out[4:0] indicates local error type. Priority
of error reporting (for the case of concurrent errors) is
noted.
Note: This signal may not work for all PCIe Link Width/
Speed configurations. Do not rely solely on this signal to
indicate an error. Alternatively, you can decode AER
register to accurately detect errors.
pcie0_cfg_rx_pm_state
pcie1_cfg_rx_pm_state
O
2
Current RX Active State Power Management L0s State:
Encoding is listed below and valid when cfg_ltssm_state is
indicating L0:
•
RX_NOT_IN_L0s = 0
•
RX_L0s_ENTRY = 1
•
RX_L0s_IDLE = 2
•
RX_L0s_FTS = 3
pcie0_cfg_tx_pm_state
pcie1_cfg_tx_pm_state
O
2
Current TX Active State Power Management L0s State:
Encoding is listed below and valid when cfg_ltssm_state is
indicating L0:
•
TX_NOT_IN_L0s = 0
•
TX_L0s_ENTRY = 1
•
TX_L0s_IDLE = 2
•
TX_L0s_FTS = 3
Chapter 3: Product Specification
PG346 (v3.3) November 16, 2022
CPM Mode for PCI Express
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