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Texas Instruments TMS320C6670, Data Manual

The Texas Instruments TMS320C6670 is a powerful multi-core digital signal processor. Get all the in-depth technical information you need with the Data Manual, available for free download on our manualshive.com. This comprehensive manual provides detailed instructions on maximizing the potential of your TMS320C6670 processor.

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Multicore Fixed and Floating-Point System-on-Chip

Copyright 2012 Texas Instruments Incorporated

List of Figures

7

SPRS689D—March 2012

TMS320C6670

www.ti.com

Figure 7-5

Soft/Hard Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Figure 7-6

Boot Configuration Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Figure 7-7

Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Figure 7-8

PLL Secondary Control Register (SECCTL)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Figure 7-9

PLL Controller Divider Register (PLLDIVn)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Figure 7-10

PLL Controller Clock Align Control Register (ALNCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Figure 7-11

PLLDIV Divider Ratio Change Status Register (DCHANGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Figure 7-12

SYSCLK Status Register (SYSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Figure 7-13

Reset Type Status Register (RSTYPE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Figure 7-14

Reset Control Register (RSTCTRL)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Figure 7-15

Reset Configuration Register (RSTCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Figure 7-16

Reset Isolation Register (RSISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Figure 7-17

Main PLL Control Register (MAINPLLCTL0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Figure 7-18

Main PLL Control Register (MAINPLLCTL1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Figure 7-19

Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Figure 7-20

Main PLL Transition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Figure 7-21

DDR3 PLL Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Figure 7-22

DDR3 PLL Control Register (DDR3PLLCTL0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Figure 7-23

DDR3 PLL Control Register 1 (DDR3PLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Figure 7-24

DDR3 PLL DDRCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

Figure 7-25

PASS PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Figure 7-26

PASS PLL Control Register (PASSPLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Figure 7-27

PASS PLL Control Register 1 (PASSPLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

Figure 7-28

PASS PLL Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Figure 7-29

Interrupt Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

Figure 7-30

NMI and LRESET Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

Figure 7-31

Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

Figure 7-32

Programmable Range n Start Address Register (PROGn_MPSAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Figure 7-33

Programmable Range n End Address Register (PROGn_MPEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Figure 7-34

Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Figure 7-35

I

2

C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

Figure 7-36

I

2

C Receive Timings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

Figure 7-37

I

2

C Transmit Timings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

Figure 7-38

SPI Master Mode Timing Diagrams — Base Timings for 3-Pin Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

Figure 7-39

SPI Additional Timings for 4-Pin Master Mode with Chip Select Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

Figure 7-40

HyperLink Station Management Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

Figure 7-41

HyperLink Station Management Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

Figure 7-42

HyperLink Station Management Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

Figure 7-43

UART Receive Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Figure 7-44

UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Figure 7-45

UART Transmit Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Figure 7-46

UART RTS (Request-to-Send Output) – Autoflow Timing Waveform  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Figure 7-47

MACID1 Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Figure 7-48

MACID2 Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Figure 7-49

RFTCLK Select Register (CPTS_RFTCLK_SEL)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

Figure 7-50

MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Figure 7-51

MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Figure 7-52

Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

Figure 7-53

GPIO Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

Figure 7-54

AIF2 RP1 Frame Synchronization Clock Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

Figure 7-55

AIF2 RP1 Frame Synchronization Burst Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

Figure 7-56

AIF2 Physical Layer Synchronization Pulse Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

Figure 7-57

AIF2 Radio Synchronization Pulse Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

Figure 7-58

AIF2 Timer External Frame Event Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

Summary of Contents for TMS320C6670

Page 1: ...ure Number SPRS689D March 2012 PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of Texas Instruments standard warranty Production processi...

Page 2: ...Updated footnote on AIF jitter value to 4 ps RMS B August 2011 Revised the INTC1 Events Input table description for BWADJ field and power sequencing timing tables and diagrams Removed all mentions of...

Page 3: ...iguration Register 72 3 3 3 JTAG ID JTAGID Register Description 73 3 3 4 Kicker Mechanism KICK0 and KICK1 Register 73 3 3 5 LRESETNMI PIN Status LRSTNMIPINSTAT Register 73 3 3 6 LRESETNMI PIN Status C...

Page 4: ...t Priority 125 7 4 6 Reset Controller Register 125 7 4 7 Reset Electrical Data Timing 126 7 5 Main PLL and the PLL Controller 128 7 5 1 Main PLL Controller Device Specific Information 129 7 5 2 PLL Co...

Page 5: ...t Ethernet GbE Switch Subsystem 207 7 20 Management Data Input Output MDIO 209 7 21 Timers 210 7 21 1 Timers Device Specific Information 210 7 21 2 Timers Electrical Data Timing 210 7 22 Rake Search A...

Page 6: ...IN Status Register LRSTNMIPINSTAT 73 Figure 3 5 LRESETNMI PIN Status Clear Register LRSTNMIPINSTAT_CLR 74 Figure 3 6 Reset Status Register RESET_STAT 75 Figure 3 7 Reset Status Clear Register RESET_ST...

Page 7: ...nterrupt Topology 156 Figure 7 30 NMI and LRESET Timing 178 Figure 7 31 Configuration Register CONFIG 187 Figure 7 32 Programmable Range n Start Address Register PROGn_MPSAR 189 Figure 7 33 Programmab...

Page 8: ...Figures Copyright2012TexasInstrumentsIncorporated SPRS689D March 2012 Multicore Fixed and Floating Point System on Chip TMS320C6670 www ti com Figure 7 59 Trace Timing 217 Figure 7 60 JTAG Test Port T...

Page 9: ...73 Table 3 6 LRESETNMI PIN Status Register Field Descriptions 74 Table 3 7 LRESETNMI PIN Status Clear Register Field Descriptions 74 Table 3 8 Reset Status Register Field Descriptions 75 Table 3 9 Re...

Page 10: ...r SRIO HyperLink PCIe Clock Input Timing Requirements 139 Table 7 27 DDR3 PLL Control Register 0 Field Descriptions 143 Table 7 28 DDR3 PLL Control Register 1 Field Descriptions DDR3PLLCTL1 143 Table...

Page 11: ...200 Table 7 69 SPI Switching Characteristics 200 Table 7 70 HyperLink Peripheral Timing Requirements 203 Table 7 71 HyperLink Peripheral Switching Characteristics 203 Table 7 72 UART Timing Requiremen...

Page 12: ...12 List of Tables Copyright2012TexasInstrumentsIncorporated SPRS689D March 2012 Multicore Fixed and Floating Point System on Chip TMS320C6670 www ti com...

Page 13: ...te Coprocessor WCDMA HSPA TD SCDMA LTE and WiMAX Uplink and Downlink Bit Processing Includes Encoding Rate Matching Dematching Segmentation Multiplexing and More Supports Up To 914 Mbps for LTE and 40...

Page 14: ...ncluding WCDMA HSPA HSPA TD SCDMA GSM TDD LTE FDD LTE and WiMAX Even with aggregate data rates for 20 MHz LTE systems above 400 Mbps per sector the C6670 can support two sectors running at full rate T...

Page 15: ...architecture solutions provide developers with a range of software and hardware compatible devices to minimize development time and maximize reuse across all base station platforms from Femto to Macro...

Page 16: ...1 1 Functional Block Diagram 4 Cores 1 0 GHz 1 2 GHz C66x CorePac C6670 MSMC 2MB MSM SRAM 64 Bit DDR3 EMIF BCP TCP3e 3 3 Coprocessors VCP2 4 Power Management Debug Trace Boot ROM Semaphore Memory Subs...

Page 17: ...configurable internal clock source CPU 6 clock frequency Eight 64 bit or Sixteen 32 bit General Purpose Input Output Port GPIO 16 Encoder Decoder Coprocessors VCP2 clock source CPU 3 clock frequency...

Page 18: ...e S and L units perform a general set of arithmetic logical and branch functions The D units primarily load data from memory to the register file and store results from the register file into memory E...

Page 19: ...ge of the larger operands instructions were also added to double the number of these conversions that can be done The L unit also has additional instructions for logical AND and OR instructions as wel...

Page 20: ...s Figure 2 1 CPU DSP Core Data Paths Data Path B Data Path A D1 src2 src1 dst S1 src1 src2 dst L1 dst src1 src2 D2 src2 Register File B B0 B1 B2 B31 Register File A A0 A1 A2 A31 src1 dst S2 L2 src1 sr...

Page 21: ...ed 01D1 8000 01D1 807F 0 01D1 8000 0 01D1 807F 128 Tracer 3 01D1 8080 01D1 FFFF 0 01D1 8080 0 01D1 FFFF 32K 128 Reserved 01D2 0000 01D2 007F 0 01D2 0000 0 01D2 007F 128 Tracer 4 01D2 0080 01D2 7FFF 0...

Page 22: ...AC_A GCCP 0 control 0214 0000 0215 FFFF 0 0214 0000 0 0215 FFFF 128K RAC_A GCCP 1 control 0216 0000 0217 FFFF 0 0216 0000 0 0217 FFFF 128K Reserved 0218 0000 0218 7FFF 0 0218 0000 0 0218 7FFF 32K TAC...

Page 23: ...0 0229 007F 128 Reserved 0229 0080 0229 FFFF 0 0229 0080 0 0229 FFFF 64K 128 Reserved 022A 0000 022A 007F 0 022A 0000 0 022A 007F 128 Reserved 022A 0080 022A FFFF 0 022A 0080 0 022A FFFF 64K 128 Rese...

Page 24: ...0 0247 FFFF 0 0247 4000 0 0247 FFFF 48K Reserved 0248 0000 0248 3FFF 0 0248 0000 0 0248 3FFF 16K Reserved 0248 4000 0248 FFFF 0 0248 4000 0 0248 FFFF 48K Reserved 0249 0000 0249 3FFF 0 0249 0000 0 024...

Page 25: ...8000 0 0273 FFFF 96K Reserved 02740000 0274 7FFF 0 02740000 0 0274 7FFF 32K EDMA3 channel controller EDMA3CC2 0274 8000 0275 FFFF 0 0274 8000 0 0275 FFFF 96K Reserved 0276 0000 0276 03FF 0 0276 0000 0...

Page 26: ...0 0285 FFFF 32K Reserved 0286 0000 028F FFFF 0 0286 0000 0 028F FFFF 640K Reserved 0290 0000 0290 0FFF 0 0290 0000 0 0290 0FFF 4K Serial RapidIO SRIO configuration 0290 8000 029F FFFF 0 0290 8000 0 02...

Page 27: ...F FFFF 5M Reserved 14E0 0000 14E0 7FFF 0 14E0 0000 0 14E0 7FFF 32K Reserved 14E0 8000 14EF FFFF 0 14E0 8000 0 14EF FFFF 1M 32K Reserved 14F0 0000 14F0 7FFF 0 14F0 0000 0 14F0 7FFF 32K Reserved 14F0 80...

Page 28: ...2100 01FF 1 0000 0000 1 0000 01FF 512 DDR3 EMIF configuration 2100 0200 213F FFFF 0 2100 0200 0 213F FFFF 4M 256 Reserved 2140 0000 2140 00FF 0 2140 0000 0 2140 00FF 256 HyperLink config 2140 0400 217...

Page 29: ...0 0 343F FFFF 384K Reserved 3440 0000 347F FFFF 0 3440 0000 0 347F FFFF 4M Reserved 3480 0000 34BF FFFF 0 3480 0000 0 34BF FFFF 4M Reserved 34C0 0000 34C2 FFFF 0 34C0 0000 0 34C2 FFFF 192K TAC data 34...

Page 30: ...ePac performs any authentication and decryption required on the bootloaded image prior to beginning execution The boot process performed by the C66x CorePac in public ROM boot and secure ROM boot is d...

Page 31: ...e master can disable the message mode by writing to the boot table and generating a boot restart Figure 2 3 No Boot Configuration Fields 9 8 7 6 5 4 3 Sub Mode Reserved Table 2 4 No Boot Configuration...

Page 32: ...output frequency of the PLL must be 1 25 GBs 0 8 for input clock of 156 25 MHz 1 5 for input clock of 250 MHz 2 4 for input clock of 312 5 MHz 3 Reserved 7 6 Ext connection External connection mode 0...

Page 33: ...64 0b0100 16 16 64 64 0b0101 16 32 64 64 0b0110 32 32 64 64 0b0111 32 32 64 128 0b1000 64 64 128 256 0b1001 4 128 128 128 0b1010 4 128 128 256 0b1011 4 128 256 256 0b1100 256 256 0b1101 512 512 0b111...

Page 34: ...alue in bits 8 5 For Ex if bits 8 5 0 then the device will listen to I 2 C bus address 0x19 4 3 Reserved Reserved End of Table 2 10 Figure 2 9 SPI Device Configuration Fields 12 11 10 9 8 7 6 5 4 3 Mo...

Page 35: ...ation of the PLL controller module see the Phase Locked Loop PLL Controller for KeyStone Devices User Guide in 2 9 Related Documentation from Texas Instruments on page 66 Figure 2 10 HyperLink Boot De...

Page 36: ...o current boot methods as well as the definition of a completely customized boot 2 6 Terminals 2 6 1 Package Terminals Figure 2 11 shows the TMS320C6670 CYP ball grid array package bottom view Figure...

Page 37: ...TXN1 PCIETXP1 VSS VSS AE VSS CVDD1 VSS VDDT2 RSV17 VDDR3 VSS RSV15 VSS VDDT2 VDDR4 VDDT2 VSS RSV16 VDDR2 AD CVDD1 VSS CVDD1 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS CORESEL2 AC VSS DVDD18...

Page 38: ...03 EMU01 AF RSV22 EXTFRAME EVENT GPIO05 GPIO03 GPIO12 GPIO09 LRESET RESETFULL DVDD18 EMU07 EMU04 DVDD18 EMU02 EMU00 AE RSV23 SDA RESETSTAT GPIO02 GPIO11 GPIO15 RSV12 PACLKSEL VSS EMU05 TRST VSS TDI TC...

Page 39: ...VDD1 VSS CVDD VSS CVDD1 VSS CVDD1 RSV11 RSV08 RSV09 AVDDA2 VSS RSV06 VSS J VSS CVDD VSS CVDD VSS CVDD VSS RSV10 PTV15 DVDD18 DDRSL RATE1 DDRSL RATE0 RSV07 DDRCLKN H DVDD15 VSS DVDD15 VSS DVDD15 VSS DV...

Page 40: ...DD1 VSS CVDD1 VSS CVDD1 VSS CVDD1 VSS CVDD1 VSS CVDD VSS CVDD1 VSS H CVDD1 VSS CVDD1 VSS CVDD1 VSS CVDD1 VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD G VSS DVDD15 VSS DVDD15 VSS CVDD1 VSS DVDD15 VSS DVDD15 VS...

Page 41: ...pins and pullup pulldown resistors see chapter 3 Device Configuration on page 67 Use the symbol definitions in Table 2 14 when reading Table 2 15 Table 2 14 I O Functional Symbol Definitions Function...

Page 42: ...timer Boot Configuration Pins LENDIAN AJ20 IOZ Up Endian configuration pin pin shared with GPIO 0 BOOTMODE00 AG18 IOZ Down See Section 2 4 Boot Modes Supported and PLL Settings on page 30 for more de...

Page 43: ...PA sub system PLL HOUT AC18 OZ Up Interrupt output pulse created by IPCGRH NMI AC25 I Up Non maskable Interrupt LRESET AE22 I Up Local Reset LRESETNMIEN AC20 I Up Enable for core selects CORESEL0 AH15...

Page 44: ...IOZ DDRDQS2N B24 IOZ DDRDQS3P A21 IOZ DDRDQS3N B21 IOZ DDRDQS4P A9 IOZ DDRDQS4N B9 IOZ DDRDQS5P B6 IOZ DDRDQS5N A6 IOZ DDRDQS6P B3 IOZ DDRDQS6N A3 IOZ DDRDQS7P D1 IOZ DDRDQS7N C1 IOZ DDRDQS8P A19 IOZ...

Page 45: ...B28 IOZ DDRD06 E26 IOZ DDRD07 F25 IOZ DDRD08 F24 IOZ DDRD09 E24 IOZ DDRD10 E25 IOZ DDRD11 D25 IOZ DDRD12 D26 IOZ DDRD13 C26 IOZ DDRD14 B26 IOZ DDRD15 A26 IOZ DDRD16 F23 IOZ DDRD17 F22 IOZ DDRD18 D24 I...

Page 46: ...Z DDRD41 D7 IOZ DDRD42 E7 IOZ DDRD43 C7 IOZ DDRD44 B7 IOZ DDRD45 E6 IOZ DDRD46 D6 IOZ DDRD47 C6 IOZ DDRD48 C5 IOZ DDRD49 A5 IOZ DDRD50 B4 IOZ DDRD51 A4 IOZ DDRD52 D4 IOZ DDRD53 E4 IOZ DDRD54 C4 IOZ DD...

Page 47: ...DDRRAS C10 OZ DDR EMIF row address strobe DDRWE E12 OZ DDR EMIF write enable DDRCKE0 D11 OZ DDR EMIF clock enables DDRCKE1 E18 OZ DDRCLKOUTP0 A12 OZ DDR EMIF output clocks to drive SDRAMs one clock p...

Page 48: ...IOZ Up EMU16 AH27 IOZ Up EMU17 AJ26 IOZ Up EMU18 AH25 IOZ Up General Purpose Input Output GPIO GPIO00 AJ20 IOZ Up General purpose input output These GPIO pins have secondary functions assigned to them...

Page 49: ...CLK V3 O Down Serial HyperLink sideband signals MCMRXFLDAT W3 O Down MCMTXFLCLK Y1 I Down MCMTXFLDAT Y2 I Down MCMRXPMCLK AA3 I Down MCMRXPMDAT Y3 I Down MCMTXPMCLK AA2 O Down MCMTXPMDAT AA1 O Down MC...

Page 50: ...ORXP1 AH9 I RIORXN2 AJ7 I RIORXP2 AJ8 I RIORXN3 AH6 I RIORXP3 AH7 I RIOTXN0 AG11 O Serial RapidIO transmit data 4 links RIOTXP0 AG10 O RIOTXN1 AF9 O RIOTXP1 AF10 O RIOTXN2 AG7 O RIOTXP2 AG8 O RIOTXN3...

Page 51: ...O Reserved leave unconnected RSV05 W27 O Reserved leave unconnected RSV06 J28 O Reserved leave unconnected RSV07 H28 O Reserved leave unconnected RSV08 J24 A Reserved connect to GND RSV09 J25 A Reserv...

Page 52: ...AE11 1 5 SRIO SerDes regulator supply VDDR5 R25 1 5 AIF SerDes regulator supply VDDR6 N25 VDDT1 M7 N6 P7 R6 T7 V7 W6 Y7 1 0 HyperLink SerDes termination supply VDDT2 AC6 AC8 AC10 AC12 AC14 AD5 AD7 AD...

Page 53: ...P13 P15 P17 P19 CVDD P21 R8 R10 R12 R14 R16 R18 R20 R22 T9 T11 T13 T15 T17 T19 T21 U8 U10 U12 U14 U16 U18 U20 U22 V9 V11 V13 V15 V17 V19 V21 V23 CVDD W8 W10 W18 W20 W22 Y9 Y19 Y21 Y23 AA8 AA10 AA12 AA...

Page 54: ...QS1P A27 DDRDQS2N B24 DDRDQS2P A24 DDRDQS3N B21 DDRDQS3P A21 DDRDQS4N B9 DDRDQS4P A9 DDRDQS5N A6 DDRDQS5P B6 DDRDQS6N A3 DDRDQS6P B3 DDRDQS7N C1 DDRDQS7P D1 DDRDQS8N B19 DDRDQS8P A19 DDRODT0 D13 DDROD...

Page 55: ...IETXP1 AF13 PHYSYNC AB27 POR AC19 PTV15 H24 RADSYNC AA27 RESETFULL AE23 RESETSTAT AD18 RESET AC24 RIORXN0 AJ11 RIORXN1 AH10 RIORXN2 AJ7 RIORXN3 AH6 RIORXP0 AJ10 RIORXP1 AH9 RIORXP2 AJ8 RIORXP3 AH7 RIO...

Page 56: ...Table 2 17 Terminal Functions By Signal Name Part 10 of 11 Signal Name Ball Number VSS K22 K26 K28 L2 L3 L5 L6 L7 L9 L11 L13 L15 L17 L19 L21 L23 M3 M6 M8 M10 M12 M14 M16 M18 M20 M22 M24 M27 M29 N1 N3...

Page 57: ...DDRDQS8N B20 DDRCB03 B21 DDRDQS3N B22 DDRD30 B23 DDRD21 B24 DDRDQS2N B25 VSS B26 DDRD14 B27 DDRDQS1N B28 DDRD05 B29 DVDD15 C1 DDRDQS7N C2 DDRD59 C3 DDRD55 C4 DDRD54 C5 DDRD48 C6 DDRD47 C7 DDRD43 C8 VS...

Page 58: ...08 F25 DDRD07 F26 VSS F27 DVDD15 F28 VSS F29 VSS G1 VSS G2 DVDD15 G3 VSS G4 DVDD15 G5 VSS G6 CVDD1 G7 VSS G8 DVDD15 G9 VSS G10 DVDD15 G11 VSS G12 DVDD15 G13 VSS G14 DVDD15 G15 VSS G16 DVDD15 G17 VSS G...

Page 59: ...CVDD1 L11 VSS L12 CVDD L13 VSS L14 CVDD1 L15 VSS L16 CVDD1 L17 VSS L18 CVDD L19 VSS L20 CVDD1 L21 VSS L22 CVDD1 L23 VSS L24 VDDT3 L25 RSV27 L26 AIFTXN0 L27 AIFTXN1 L28 AIFRXN0 L29 AIFRXP1 M1 MCMRXP2...

Page 60: ...VSS R20 CVDD R21 VSS R22 CVDD R23 VSS R24 VDDT3 R25 VDDR5 R26 AIFTXN2 R27 VSS R28 AIFRXN2 R29 VSS T1 VSS T2 MCMRXN0 T3 VSS T4 VSS T5 MCMTXN0 T6 VSS T7 VDDT1 T8 VSS T9 CVDD T10 VSS T11 CVDD T12 VSS T1...

Page 61: ...CMRXPMDAT Y4 RSV28 Y5 DVDD18 Y6 VSS Y7 VDDT1 Y8 VSS Y9 CVDD Y10 VSS Y11 CVDD1 Y12 VSS Y13 CVDD1 Y14 VSS Y15 CVDD1 Y16 VSS Y17 CVDD1 Y18 VSS Y19 CVDD Y20 VSS Y21 CVDD Y22 VSS Y23 CVDD Y24 VSS Y25 DVDD1...

Page 62: ...AD16 RSV23 AD17 SDA AD18 RESETSTAT AD19 GPIO02 AD19 BOOTMODE01 AD20 GPIO11 AD20 BOOTMODE10 AD21 GPIO15 AD21 PCIESSMODE1 AD22 RSV12 AD23 PACLKSEL AD24 VSS AD25 EMU05 AD26 TRST AD27 VSS AD28 TDI AD29 TC...

Page 63: ...all Number Signal Name AH6 RIORXN3 AH7 RIORXP3 AH8 VSS AH9 RIORXP1 AH10 RIORXN1 AH11 VSS AH12 PCIERXN1 AH13 PCIERXP1 AH14 VSS AH15 CORESEL0 AH16 SRIOSGMIICLKN AH17 PCIECLKP AH18 PASSCLKN AH19 GPIO07 A...

Page 64: ...art numbers of all DSP devices and support tools Each DSP commercial family member has one of three prefixes TMX TMP or TMS e g TMX320CMH Texas Instruments recommends two of three possible prefix desi...

Page 65: ...in the CYP package type see the TI website www ti com or contact your TI sales representative Figure 2 17 provides a legend for reading the complete device name for any C66x DSP generation member Fig...

Page 66: ...ne Devices SPRABI2 HyperLink for KeyStone Devices User Guide SPRUGW8 Inter Integrated Circuit I 2 C for KeyStone Devices User Guide SPRUGV3 Chip Interrupt Controller CIC for KeyStone Devices User Guid...

Page 67: ...pullup pulldown resistors and situations in which external pullup pulldown resistors are required see Section 3 4 Pullup Pulldown Resistors on page 85 Table 3 1 Device Configuration Pins Configuratio...

Page 68: ...egisters Part 1 of 4 Address Start Address End Size Acronym Description 0x02620000 0x02620007 8B Reserved 0x02620008 0x02620017 16B Reserved 0x02620018 0x0262001B 4B JTAGID See section 3 3 3 0x0262001...

Page 69: ...6201A7 4B Reserved 0x026201A8 0x026201AB 4B Reserved 0x026201AC 0x026201AF 4B Reserved 0x026201B0 0x026201B3 4B Reserved 0x026201B4 0x026201B7 4B Reserved 0x026201B8 0x026201BB 4B Reserved 0x026201BC...

Page 70: ...B Reserved 0x0262031C 0x0262031F 4B Reserved 0x02620320 0x02620323 4B Reserved 0x02620324 0x02620327 4B Reserved 0x02620328 0x0262032B 4B MAINPLLCTL0 See section 7 5 Main PLL and the PLL Controller on...

Page 71: ...on from Texas Instruments on page 66 0x026203B8 0x026203BB 4B HYPERLINK_SERDES_CFGRX0 0x026203BC 0x026203BF 4B HYPERLINK_SERDES_CFGTX0 0x026203C0 0x026203C3 4B HYPERLINK_SERDES_CFGRX1 0x026203C4 0x026...

Page 72: ...DE 1 0 PCIe mode selection pins 00b PCIe in end point mode 01b PCIe in legacy end point mode support for legacy INTx 10b PCIe in root complex mode 11b Reserved 13 1 BOOTMODE 12 0 Determines the bootmo...

Page 73: ...permissions are writable the read only MMRs are still read only The first KICK0 data is 0x83e70b13 The second KICK1 data is 0x95a4f1e0 Writing any other data value to either of these kick MMRs will lo...

Page 74: ...rved Reserved 3 LR4 CorePac3 in Local Reset 2 LR3 CorePac2 in Local Reset 1 LR31 CorePac1 in Local Reset 0 LR0 CorePac0 in Local Reset End of Table 3 6 Figure 3 5 LRESETNMI PIN Status Clear Register L...

Page 75: ...the RESET_STAT_CLR register The Reset Status Clear Register is shown in Figure 3 7 and described in Table 3 9 Figure 3 6 Reset Status Register RESET_STAT 31 30 4 3 2 1 0 GR Reserved LR3 LR2 LR1 LR0 R...

Page 76: ...0 Writing a 0 has no effect 1 Writing a 1 to the LR2 bit clears the corresponding bit in the RESET_STAT register 1 LR1 CorePac1 reset clear bit 0 Writing a 0 has no effect 1 Writing a 1 to the LR1 bi...

Page 77: ...CorePac The C6670 has four NMIGRx registers NMIGR0 through NMIGR3 The NMIGR0 register generates an NMI event to CorePac0 the NMIGR1 register generates an NMI event to CorePac1 and so on Writing a 1 t...

Page 78: ...can be a source for these registers as this is completely controlled by software Any master that has access to BOOTCFG module space can write to these registers The IPC Generation Register is shown i...

Page 79: ...upt output pulse created by IPCGRH is driven on a device pin host interrupt event output HOUT The host interrupt output pulse should be stretched It should be asserted for 4 bootcfg clock cycles CPU 6...

Page 80: ...served 0 IPCG Reads return 0 Writes 0 No effect 1 Creates an interrupt pulse on device pin host interrupt event output in HOUT pin End of Table 3 15 Figure 3 14 IPC Acknowledgement Register IPCARH 31...

Page 81: ...I0 1 TIMI1 11 TINPHSEL5 Input select for TIMER5 high 0 TIMI0 1 TIMI1 10 TINPLSEL5 Input select for TIMER5 low 0 TIMI0 1 TIMI1 9 TINPHSEL4 Input select for TIMER4 high 0 TIMI0 1 TIMI1 8 TINPLSEL4 Input...

Page 82: ...SEL0 R 0000000000000000000000000 RW 0001 0 RW 0000 Legend R Read only RW Read Write n value after reset Table 3 18 Timer Output Selection Field Description Bit Field Description 31 9 Reserved Reserved...

Page 83: ...hen OMODE 100b 001b 512 CPU 6 cycles delay between NMI local reset when OMODE 100b 010b 1024 CPU 6 cycles delay between NMI local reset when OMODE 100b 011b 2048 CPU 6 cycles delay between NMI local r...

Page 84: ...The Device Speed Register is shown below Figure 3 18 Device Speed Register DEVSPEED 31 23 22 0 DEVSPEED Reserved R n R n Legend R Read only n value after reset Table 3 20 Device Speed Register Field D...

Page 85: ...eakage currents of all the devices connected to the net as well as any internal pullup or pulldown resistors Decide a target value for the net For a pulldown resistor this should be below the lowest V...

Page 86: ...e of a peripheral and the data buses are used mainly for data transfers The C66x CorePacs the EDMA3 traffic controllers and the various system peripherals can be classified into two categories masters...

Page 87: ...Y Y Y EDMA3CC0_TC0_RD 2 2 2 2 2 2 2 2 Y Y Y Y Y EDMA3CC0_TC0_WR 2 2 2 2 2 2 2 Y Y Y Y EDMA3CC0_TC1_RD 3 3 3 3 3 3 3 Y Y Y Y Y EDMA3CC0_TC1_WR 3 3 3 3 3 3 Y Y Y Y EDMA3CC1_TC0_RD Y Y Y Y Y Y Y 5 5 5 Y...

Page 88: ...12 1 12 1 12 1 12 1 12 1 12 1 12 1 12 1 12 1 12 1 12 1 12 1 12 1 12 1 12 1 12 1 12 1 12 1 12 BCP_FFTCC_TCP3dC Master Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y EDMA3CC0_TC0_RD 2 12 2 12 2 12 2 12 2 12 2 12 EDMA3...

Page 89: ...12 12 12 12 12 12 12 12 12 12 12 12 12 12 Network Coprocessor Packet DMA MSMC_Data_Master QM_SS Packet DMA QM_SS Second DebugSS_Master 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 1...

Page 90: ...12 Y 12 12 12 12 Y Y EDMA3CC2_TC1_RD EDMA3CC2_TC1_WR EDMA3CC2_TC2_RD 12 Y 12 12 12 12 Y Y EDMA3CC2_TC2_WR 12 Y 12 12 12 12 Y Y EDMA3CC2_TC3_RD EDMA3CC2_TC3_WR SRIO Packet DMA SRIO_M 12 Y 12 12 12 12 Y...

Page 91: ...QM_SS Second M TNet_3_H CPU 3 Debug_SS M FFTC_B Packet DMA M TNet_3_D CPU 3 FFTC_A Packet DMA M RAC_B_BE0 M RAC_B_BE1 M RAC_A_BE0 M RAC_A_BE1 M TAC_FE M PCIe M TNet_3_F CPU 3 SRIO_M M Bridge_1 Bridge_...

Page 92: ...tDocumentationFeedback Figure 4 2 TeraNet 2A TeraNet 2_A CPU 2 Bridge_1 Bridge_2 Bridge_3 Bridge_4 To TeraNet_3_A Tracer_MSMC0 EDMA CC0 TC_1 M TC_0 M HyperLink M Bridge_5 Bridge_6 Bridge_7 Bridge_8 Fr...

Page 93: ...93 SPRS689D March 2012 TMS320C6670 www ti com Submit Documentation Feedback Figure 4 3 TeraNet 3P and 3M and 2M TeraNet 3P CPU 3 BCP_CFG S FFTC_CFG S TCP3D_CFG S MPU TeraNet 3M CPU 3 MPU_CFG S TCP3d_...

Page 94: ...Us present in the specific device TeraNet 3P_A CPU 3 To TeraNet_3P_Tracer Bridge_12 Bridge_13 Bridge_14 From TeraNet_3_A CorePac_0 M M CorePac_1 CorePac_2 M M CorePac_3 TETB Debug_SS TETB core 4 CC2 S...

Page 95: ...S689D March 2012 TMS320C6670 www ti com Submit Documentation Feedback Figure 4 5 TeraNet 3P_B From TeraNet_3P_A TeraNet 3P_B CPU 3 S AIF2 NETCP S FFTC_B S FFTC_A S TNet_3P_G CPU 3 TCP3d_B S TCP3d_A S...

Page 96: ...racer TeraNet 6P_B CPU 6 Bridge_20 From TeraNet_3P_B GPIO S SmartReflex S Timer 8 S CIC 3 4 S PLL_CTL S PSC S BOOTCFG S UART S I C 2 S Debug_SS S TeraNet 3P_Tracer CPU 3 Tracer_SM M Tracer_DDR M Trace...

Page 97: ...lso have internal registers to define the priority level of their initiated transactions The Packet DMA secondary port is one master port that does not have priority allocation register inside the IP...

Page 98: ...idth management for resources local to the CorePac Figure 5 1 shows a block diagram of the C66x CorePac Figure 5 1 C66x CorePac Block Diagram Boot Controller LPSC PLLC GPSC L1 S1 M1 xx xx D1 D2 M2 xx...

Page 99: ...uration Register L1PMODE and the L1DMODE field of the L1D Configuration Register L1DCFG of the C66x CorePac L1D is a two way set associative cache while L1P is a direct mapped cache The on chip bootlo...

Page 100: ...vice is as follows Region 0 size is 0K bytes disabled Region 1 size is 32K bytes with no wait states Figure 5 3 shows the available SRAM cache configurations for L1D Figure 5 3 L1D Memory Configuratio...

Page 101: ...mix of the two The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register L2CFG of the C66x CorePac Figure 5 4 shows the available SRAM...

Page 102: ...SRAM is always configured as all SRAM When configured as a shared L2 its contents can be cached in L1P and L1D When configured in shared L3 mode it s contents can be cached in L2 also For more detail...

Page 103: ...granting access to the highest priority requestor The following four resources are managed by the Bandwidth Management control hardware Level 1 Program L1P SRAM Cache Level 1 Data L1D SRAM Cache Leve...

Page 104: ...exas Instruments on page 66 5 5 CorePac Revision The version and revision of the C66x CorePac can be read from the CorePac Revision ID Register MM_REVID located at address 0181 2000h The MM_REVID regi...

Page 105: ...V to 1 3 V SerDes 0 3 V to CVDD1 0 3 V Output voltage VO range LVCMOS 1 8 V 0 3 V to DVDD18 0 3 V DDR3 0 3 V to 2 45 V I2 C 0 3 V to 2 45 V SerDes 0 3 V to CVDD1 0 3 V Operating case temperature range...

Page 106: ...rtReflex core supply voltage between 0 9 V and 1 1 V set from the factory for each individual device 0 9 1 1 SRVnom 1 05 V CVDD1 Core supply 0 95 1 1 05 V DVDD18 1 8 V supply I O voltage 1 71 1 8 1 89...

Page 107: ...does not have a VOH Minimum VOL Low level output voltage LVCMOS 1 8 V IO IOL 0 45 V DDR3 0 4 I 2 C IO 3 mA pulled up to 1 8 V 0 4 II 3 3 II applies to input only pins and bidirectional pins For input...

Page 108: ...LTCORECLK P N PLL input buffer SRIOSGMIICLK P N SerDes PLL input buffer DDRCLK P N PLL input buffer PCIECLK P N SerDes PLL input buffer MCMCLK P N SerDes PLL input buffer PASSCLK P N PLL input buffer...

Page 109: ...upply 1 0 V Filtered version of CVDD1 Special considerations for noise Filter is not needed if SGMII SRIO PCIE is not in use VDDT3 AIF SerDes termination supply 1 0 V Filtered version of CVDD1 Special...

Page 110: ...void internal oscillation the clock inputs should be removed from the high impedance state shortly after CVDD is present If a clock input is not used it must be held in a static state To accomplish th...

Page 111: ...d after the rising edge of POR but may be held low for longer periods if necessary The configuration bits shared with the GPIO pins will be latched on the rising edge of RESETFULL and must meet the se...

Page 112: ...R goes high specified by t6 3 Filtered versions of 1 8 V can ramp simultaneously with DVDD18 RESETSTAT is driven low once the DVDD18 supply is available All LVCMOS input and bidirectional pins must no...

Page 113: ...Sequencing The timing diagram for IO before core power sequencing is shown in Figure 7 2 and defined in Table 7 3 Note TI recommends a maximum of 100 ms between one power rail being valid and the next...

Page 114: ...be driven high anytime after DVDD18 is at a valid level 2b CVDD core AVS ramps up 3a CVDD1 core constant ramps at the same time or following CVDD Although ramping CVDD1 and CVDD simultaneously is perm...

Page 115: ...ng DDRCLK None Must be present 16 sec before POR transitions high SYSCLK CORECLKSEL 0 SYSCLK used to clock the core PLL It must be present 16 sec before POR transitions high CORECLKSEL 1 SYSCLK used o...

Page 116: ...e voltage to be optimized based on the process corner of the device This requires a voltage regulator for each TMS320C6670 device To guarantee maximizing performance and minimizing power consumption o...

Page 117: ...k s Note Power Connection 0 Most peripheral logic Cannot be disabled Always on 1 Per core TETB and system TETB RAMs can be powered down Software control 2 Network Coprocessor Logic can be powered down...

Page 118: ...ays on 3 TCP3e Software control 4 VCP2_A Software control 5 Debug subsystem and tracers Software control 6 Per core TETB and system TETB Software control 7 Packet Accelerator Software control 8 Ethern...

Page 119: ..._B and TAC 0x224 PDSTAT9 Power Domain Status Register 9 FFTC_A and FFTC_B 0x228 PDSTAT10 Power Domain Status Register 10 AIF2 0x22C PDSTAT11 Power Domain Status Register 11 TCP3d_A 0x230 PDSTAT12 Powe...

Page 120: ...MDSTAT11 Module Status Register 11 SRIO 0x830 MDSTAT12 Module Status Register 12 HyperLink 0x834 MDSTAT13 Module Status Register 13 Reserved 0x838 MDSTAT14 Module Status Register 14 MSMC RAM 0x83C MDS...

Page 121: ...Module Control Register 15 RAC_A and RAC_B 0xA40 MDCTL16 Module Control Register 16 TAC 0xA44 MDCTL17 Module Control Register 17 FFTC_A and FFTC_B 0xA48 MDCTL18 Module Control Register 18 AIF2 0xA4C M...

Page 122: ...enabled Other resets do not affect the state of the PLL or the dividers in the PLL Controller Table 7 9 Reset Types Type Initiator Effect s Power on Reset POR pin RESETFULL pin Resets the entire chip...

Page 123: ...L controllers are allowed to finish their current cycles and then paused for 10 cycles of their respective system reference clocks After the pause the system clocks are restarted at their default divi...

Page 124: ...affected PLLs also remain locked 2 After device initialization is complete the RESETSTAT pin is deasserted driven high In addition the PLL Controllers pause their system clocks for about 8 cycles At...

Page 125: ...L processes only the highest priority reset request The reset request priorities are as follows high to low Power on reset Hard soft reset 7 4 6 Reset Controller Register The reset controller register...

Page 126: ...ck frequency in ns No Min Max Unit RESETFULL Pin Reset 1 tw RESETFULL Pulse width pulse width RESETFULL low 500C ns Soft Hard Reset 2 tw RESET Pulse width pulse width RESET low 500C ns End of Table 7...

Page 127: ...0 www ti com Submit Documentation Feedback Figure 7 6 Boot Configuration Timing Table 7 12 Boot Configuration Timing Requirements 1 See Figure 7 6 1 C 1 SYSCLK1 clock frequency in ns No Min Max Unit 1...

Page 128: ...exas Instruments on page 66 The Main PLL is controlled by the standard PLL Controller The PLL Controller manages the clock ratios alignment and gating for the system clocks to the device Figure 7 7 sh...

Page 129: ...iming requirements see Section 7 5 5 Main PLL Controller SRIO HyperLink PCIe Clock Input Electrical Data Timing CAUTION The PLL Controller module as described in the see the Phase Locked Loop PLL Cont...

Page 130: ...g the values set in the PLLM and PLLD fields in the MAINPLLCTL0 Register In bypass mode PLL input is fed directly out as SYSCLK1 All hosts must hold off accesses to the DSP while the frequency of its...

Page 131: ...oller Registers Including Reset Controller Part 1 of 2 Hex Address Range Acronym Register Name 0231 0000 0231 00E3 Reserved 0231 00E4 RSTYPE Reset Type Status Register Reset Controller 0231 00E8 RSTCT...

Page 132: ...of Table 7 14 Figure 7 8 PLL Secondary Control Register SECCTL 31 24 23 22 19 18 0 Reserved BYPASS OUTPUT DIVIDE Reserved R 0000 0000 RW 1 RW 0001 RW 001 0000 0000 0000 0000 Legend R W Read Write R R...

Page 133: ...f Figure 7 9 0 Divider n is disabled 1 No clock output Divider n is enabled 14 8 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 7 0 RATIO D...

Page 134: ...0 R W 0 R 0 R W 0 R 0 Legend R W Read Write R Read only n value after reset for reset value Table 7 18 PLLDIV Divider Ratio Change Status Register Field Descriptions Bit Field Description 31 8 6 5 3...

Page 135: ...R 0 R 0 R 0 Legend R Read only n value after reset Table 7 20 Reset Type Status Register Field Descriptions Bit Field Description 31 29 Reserved Reserved Read only Always reads as 0 Writes have no ef...

Page 136: ...in Table 7 22 Figure 7 14 Reset Control Register RSTCTRL 31 17 16 15 0 Reserved SWRST KEY R 0x0000 R W 0x 1 1 Writes are conditional based on valid key R W 0x0003 Legend R Read only n value after rese...

Page 137: ...ide in 2 9 Related Documentation from Texas Instruments on page 66 The Reset Isolation register RSTCTRL is shown in Figure 7 16 and described in Table 7 23 11 4 Reserved Reserved 3 2 1 0 WDTYPE3 WDTYP...

Page 138: ...0101 RW 0000 0 RW 0000000 RW 000000 RW 000000 Legend RW Read Write n value after reset Table 7 24 Main PLL Control Register MAINPLLCTL0 Field Descriptions Bit Field Description 31 24 BWADJ 7 0 BWADJ...

Page 139: ...SCLKN Cycle time SYSCLKN cycle time 3 25 or 6 51 or 8 138 2 ns 1 tc SYSCLKP Cycle time SYSCLKP cycle time 3 25 or 6 51 or 8 138 ns 3 tw SYSCLKN Pulse width SYSCLKN high 0 45 tc 0 55 tc ns 2 tw SYSCLKN...

Page 140: ...KN cycle time 3 2 or 4 or 6 4 ns 1 tc MCMCLKP Cycle time MCMCLKP cycle time 3 2 or 4 or 6 4 ns 3 tw MCMCLKN Pulse width MCMCLKN high 0 45 tc MCMCLKN 0 55 tc MCMCLKN ns 2 tw MCMCLKN Pulse width MCMCLKN...

Page 141: ...tone Devices in 2 9 Related Documentation from Texas Instruments on page 66 for detailed recommendations 2 If AIF2 is being used then SYSCLK N P can be programmed only to fixed values if AIF2 is not b...

Page 142: ...imize the spacing between switching signal traces and the PLL external components C1 C2 and the EMI Filter Figure 7 21 DDR3 PLL Block Diagram 7 6 1 DDR3 PLL Control Registers The DDR3 PLL which is use...

Page 143: ...ble 7 27 DDR3 PLL Control Register 0 Field Descriptions Bit Field Description 31 24 BWADJ 7 0 BWADJ 11 8 and BWADJ 7 0 are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers BWADJ 11 0 should be program...

Page 144: ...PASS PLL as either the output of Main PLL mux or the PASSCLK clock reference sources When coming out of power on reset PASS PLL comes out in a bypass mode and needs to be programmed to a valid freque...

Page 145: ...l Registers The PASS PLL which is used to drive the Network Coprocessor does not use a PLL controller PASS PLL can be controlled using the PAPLLCTL0 and PAPLLCTL1 registers located in Bootcfg module T...

Page 146: ...d BWADJ 7 0 are located in PASSPLLCTL0 and PASSPLLCTL1 registers BWADJ 11 0 should be programmed to a value equal to half of PLLM 12 0 value round down if PLLM has an odd value Example If PLLM 15 then...

Page 147: ...he rest of the bits including the reserved bits are not affected 7 7 4 PASS PLL Input Clock Electrical Data Timing Figure 7 28 PASS PLL Timing Table 7 32 PASS PLL Timing Requirements See Figure 7 28 a...

Page 148: ...imized to be used for transfers to from within the MSMC and DDR 3 subsytems The others are used for the remaining traffic Each EDMA3 channel controller includes the following features Fully orthogonal...

Page 149: ...ocumentation from Texas Instruments on page 66 7 8 2 EDMA3 Channel Controller Configuration Table 7 33 provides the configuration for each of the EDMA3 channel controllers present on the device 7 8 3...

Page 150: ...nts on page 66 Table 7 34 EDMA3 Transfer Controller Configuration Parameter EDMA3CC0 EDMA3CC1 EDMA3CC2 TC0 TC1 TC0 TC1 TC2 TC3 TC0 TC1 TC2 TC3 FIFOSIZE 1024 bytes 1024 bytes 1024 bytes 512 bytes 1024...

Page 151: ...adio timing sync event 4 15 AIF_SEVT5 AIF radio timing sync event 5 16 AIF_SEVT6 AIF radio timing sync event 6 17 AIF_SEVT7 AIF radio timing sync event 7 18 SEMINT0 Semaphore interrupt 19 SEMINT1 Sema...

Page 152: ...58 CIC1_OUT15 Interrupt Controller output 59 CIC1_OUT16 Interrupt Controller output 60 CIC1_OUT17 Interrupt Controller output 61 CIC1_OUT18 Interrupt Controller output 62 CIC1_OUT19 Interrupt Controll...

Page 153: ...1_OUT26 Interrupt Controller output 40 CIC1_OUT27 Interrupt Controller output 41 CIC1_OUT28 Interrupt Controller output 42 CIC1_OUT29 Interrupt Controller output 43 CIC1_OUT30 Interrupt Controller out...

Page 154: ...012 Multicore Fixed and Floating Point System on Chip TMS320C6670 www ti com SubmitDocumentationFeedback 62 FFTC_C_ERROR2 FFTC_C Error event and FFTC_C debug event 63 FFTC_C_ERROR3 FFTC_C Error event...

Page 155: ...ffload the C66x CorePac interrupt selector This is accomplished through Chip Interrupt Controller CIC blocks CIC 2 0 for C6670 device This is clocked using CPU 6 The event controllers consist of simpl...

Page 156: ...iner 0 output 1 EVT1 Event combiner 1 output 2 EVT2 Event combiner 2 output CIC0 CIC1 82 Common Events Hyper Link 19 Secondary Events 32 Secondary Events 10 Secondary Events 72 EDMACC only Events 45 P...

Page 157: ...rrupt 22 CIC0_OUT 64 0 10 n 7 Interrupt Controller output 23 CIC0_OUT 64 1 10 n 7 Interrupt Controller output 24 CIC0_OUT 64 2 10 n 7 Interrupt Controller output 25 CIC0_OUT 64 3 10 n 7 Interrupt Cont...

Page 158: ...ut 60 CIC0_OUT4 Interrupt Controller output 61 CIC0_OUT5 Interrupt Controller output 62 CIC0_OUT6 Interrupt Controller output 63 CIC0_OUT7 Interrupt Controller output 64 TINTLn6 Local Timer interrupt...

Page 159: ...rrupt from Side A 101 EFIINTB EFI interrupt from Side B 102 AIF_SEVT0 AIF system event 103 AIF_SEVT1 AIF system event 104 AIF_SEVT2 AIF system event 105 AIF_SEVT3 AIF system event 106 AIF_SEVT4 AIF sy...

Page 160: ...DMA3CC1 INT5 EDMA3CC1 individual completion interrupt 14 EDMA3CC1 INT6 EDMA3CC1 individual completion interrupt 15 EDMA3CC1 INT7 EDMA3CC1 individual completion interrupt 16 EDMA3CC2 EDMACC_ERRINT EDMA...

Page 161: ...cquisition has been completed 66 TETBOVFLINT Overflow condition occurred 67 TETBUNFLINT Underflow condition occurred 68 mdio_link_intr0 Packet Accelerator subsystem MDIO interrupt 69 mdio_link_intr1 P...

Page 162: ...r Correctable 1 bit soft error detected on SRAM read 99 MSMC_dedc_nc_error Non correctable 2 bit soft error detected on SRAM read 100 MSMC_scrub_nc_error Non correctable 2 bit soft error detected duri...

Page 163: ...INT_PASS_TXQ_PEND_27 Queue Manager Packet Accelerator pend event 140 QM_INT_PASS_TXQ_PEND_28 Queue Manager Packet Accelerator pend event 141 QM_INT_PASS_TXQ_PEND_29 Queue Manager Packet Accelerator pe...

Page 164: ...0 SmartReflex sensor interrupt 182 SmartReflex_intrreq1 SmartReflex sensor interrupt 183 SmartReflex_intrreq2 SmartReflex sensor interrupt 184 SmartReflex_intrreq3 SmartReflex sensor interrupt 185 VPN...

Page 165: ...s been completed 11 TETBHFULLINT0 TETB is half full 12 TETBFULLINT0 TETB is full 13 TETBACQINT0 Acquisition has been completed 14 TETBHFULLINT1 TETB is half full 15 TETBFULLINT1 TETB is full 16 TETBAC...

Page 166: ...terrupt for QM_SS CFG 56 TRACER_QM_SS_DMA_INTD Tracer sliding time window interrupt for QM_SS slave port 57 TRACER_SEM_INTD Tracer sliding time window interrupt for Semaphore 58 SEMERR0 Semaphore inte...

Page 167: ...ction fault indicators for each system master PrivID 88 MSMC_MPF_ERROR12 Memory protection fault indicators for each system master PrivID 89 MSMC_MPF_ERROR13 Memory protection fault indicators for eac...

Page 168: ...ddressing violation interrupt and protection violation interrupt 136 Reserved 137 QM_INT_HIGH_0 QM interrupt 138 QM_INT_HIGH_1 QM interrupt 139 QM_INT_HIGH_2 QM interrupt 140 QM_INT_HIGH_3 QM interrup...

Page 169: ...TBACQINT1 TETB1 acquisition has been completed 25 TETBHFULLINT2 TETB2 is half full 26 TETBFULLINT2 TETB2 is full 27 TETBACQINT2 TETB2 acquisition has been completed 28 TETBHFULLINT3 TETB3 is half full...

Page 170: ...er64_5 interrupt high 53 TINT6L Timer64_6 interrupt low 54 TINT6H Timer64_6 interrupt high 55 TINT7L Timer64_7 interrupt low 56 TINT7H Timer64_7 interrupt high 57 Reserved 58 Reserved 59 Reserved 60 R...

Page 171: ...G3 Enable Clear Register 3 0x390 ENABLE_CLR_REG4 Enable Clear Register 4 0x394 ENABLE_CLR_REG5 Enable Clear Register 5 0x398 ENABLE_CLR_REG6 Enable Clear Register 6 0x400 CH_MAP_REG0 Interrupt Channel...

Page 172: ...P_REG37 Interrupt Channel Map Register for 148 to 148 3 0x498 CH_MAP_REG38 Interrupt Channel Map Register for 152 to 152 3 0x49c CH_MAP_REG39 Interrupt Channel Map Register for 156 to 156 3 0x4a0 CH_M...

Page 173: ...f 3 Address Offset Register Mnemonic Register Name 0x0 REVISION_REG Revision Register 0x10 GLOBAL_ENABLE_HINT_REG Global Host Int Enable Register 0x20 STATUS_SET_INDEX_REG Status Set Index Register 0x...

Page 174: ...CH_MAP_REG17 Interrupt Channel Map Register for 68 to 68 3 0x448 CH_MAP_REG18 Interrupt Channel Map Register for 72 to 72 3 0x44c CH_MAP_REG19 Interrupt Channel Map Register for 76 to 76 3 0x450 CH_MA...

Page 175: ...Table 7 44 CIC2 Registers Part 1 of 2 Address Offset Register Mnemonic Register Name 0x0 REVISION_REG Revision Register 0x10 GLOBAL_ENABLE_HINT_REG Global Host Int Enable Register 0x20 STATUS_SET_IND...

Page 176: ...er for 24 to 24 3 0x81c HINT_MAP_REG7 Host Interrupt Map Register for 28 to 28 3 0x820 HINT_MAP_REG8 Host Interrupt Map Register for 32 to 32 3 0x824 HINT_MAP_REG9 Host Interrupt Map Register for 36 t...

Page 177: ...262028F 4B IPCAR3 IPC Acknowledgement Register for CorePac3 0x02620290 0x02620293 4B Reserved Reserved 0x02620294 0x02620297 4B Reserved Reserved 0x02620298 0x0262029B 4B Reserved Reserved 0x0262029C...

Page 178: ...No Min Max Unit 1 tsu LRESET LRESETNMIENL Setup time LRESET valid before LRESETNMIEN low 12 P ns 1 tsu NMI LRESETNMIENL Setup time NMI valid before LRESETNMIEN low 12 P ns 1 tsu CORESELn LRESETNMIENL...

Page 179: ...the configuration of each MPU and the memory regions protected by each MPU Table 7 50 shows the unique Master ID assigned to each CorePac and peripherals on the device Table 7 48 MPU Default Configura...

Page 180: ...MA0_TC1 read 19 EDMA0_TC1 write 20 EDMA1_TC0 read 21 EDMA1_TC0 write 22 EDMA1_TC1 read 23 EDMA1_TC1write 24 EDMA1_TC2 read 25 EDMA1_TC2 write 26 EDMA1_TC3 read 27 EDMA1_TC3 write 28 EDMA2_TC0 read 29...

Page 181: ...for external linking RAM and the other one for the PDSP MCDM accesses 54 SRIO_M 55 HyperLink 56 to 59 Queue Manager 60 to 63 Reserved 64 to 71 AIF2 72 to 85 Reserved 86 Reserved 87 Reserved 88 to 91...

Page 182: ...orePac3 SW dependant driven by MSMC SW dependant DMA 4 AIF User Non secure DMA 5 TAC User Non secure DMA 6 RAC User Non secure DMA 7 FFTC User Non secure DMA 8 QM_SS Second User Non secure DMA 9 SRIO...

Page 183: ...tection attributes 280h PROG8_MPSAR Programmable range 8 start address 284h PROG8_MPEAR Programmable range 8 end address 288h PROG8_MPPA Programmable range 8 memory page protection attributes 290h PRO...

Page 184: ...ogrammable range 1 memory page protection attributes 220h PROG2_MPSAR Programmable range 2 start address 224h PROG2_MPEAR Programmable range 2 end address 228h PROG2_MPPA Programmable range 2 memory p...

Page 185: ...PA Programmable range 7 memory page protection attributes 280h PROG8_MPSAR Programmable range 8 start address 284h PROG8_MPEAR Programmable range 8 end address 288h PROG8_MPPA Programmable range 8 mem...

Page 186: ...rammable range 0 memory page protection attributes 300h FLTADDRR Fault address 304h FLTSTAT Fault status 308h FLTCLR Fault clear End of Table 7 55 Table 7 56 MPU4 Registers Offset Name Description 0h...

Page 187: ...MPEAR Programmable range 0 end address 208h PROG0_MPPA Programmable range 0 memory page protection attributes 210h PROG1_MPSAR Programmable range 1 start address 214h PROG1_MPEAR Programmable range 1...

Page 188: ...Field Description 31 24 ADDR_WIDTH Address alignment for range checking 0 1KB alignment 6 64KB alignment 23 20 NUM_FIXED Number of fixed address ranges 19 16 NUM_PROG Number of programmable address ra...

Page 189: ...Field Descriptions Bit Field Description 31 10 START_ADDR Start address for range n 9 0 Reserved Reserved Always read as 0 End of Table 7 59 Table 7 60 Programmable Range n Start Address Register PROG...

Page 190: ...s Register Field Descriptions Bit Field Description 31 10 END_ADDR End address for range n 9 0 Reserved Reserved Always read as 3FFh End of Table 7 61 Table 7 62 Programmable Range n End Address Regis...

Page 191: ...R W R W R W R W R W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AID4 AID3 AID2 AID1 AID0 AIDX Reserved NS EMU SR SW SX UR UW UX R W R W R W R W R W R W R R W R W R W R W R W R W R W R W Legend R Read only R W...

Page 192: ...Access granted 8 Reserved Reserved Always reads as 0 7 NS Non secure access permission 0 Only secure access allowed 1 Non secure access allowed 6 EMU Emulation debug access permission This bit is ign...

Page 193: ...FCB6 0X0003_FCB4 0X0003_FCB6 N A N A 0X03FF_FCB6 Register 3 0X03FF_FCB6 0X0003_FC80 0X0003_FCB4 N A N A N A Register 4 0X03FF_FCB6 0X0003_FCB6 0X0003_FCB4 N A N A N A Register 5 0X03FF_FCB6 N A 0X0003...

Page 194: ...iming for the DDR3 memory bus is different than on other interfaces such as I2 C or SPI For these other interfaces the device timing was specified in terms of data manual specifications and I O buffer...

Page 195: ...he Inter Integrated Circuit I2 C module provides an interface between DSP and other devices compliant with Philips Semiconductors Inter IC bus I 2 C bus specification version 2 1 and connected by way...

Page 196: ...ime Divider Register 0253 0014 ICCNT I 2 C Data Count Register 0253 0018 ICDRR I2 C Data Receive Register 0253 001C ICSAR I 2 C Slave Address Register 0253 0020 ICDXR I 2 C Data Transmit Register 0253...

Page 197: ...s 197 SPRS689D March 2012 TMS320C6670 www ti com Submit Documentation Feedback 0253 0034 ICPID1 I2 C Peripheral Identification Register 1 value 0x0000 0105 0253 0038 ICPID2 I 2 C Peripheral Identifica...

Page 198: ...the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line tr max tsu SDA SCLH 1000 25...

Page 199: ...s 18 th SDAL SCLL Hold time SDA low after SCL low for a START and a repeated START condition 4 0 6 ms 19 tw SCLL Pulse duration SCL low 4 7 1 3 ms 20 tw SCLH Pulse duration SCL high 4 0 6 ms 21 td SDA...

Page 200: ...ceive edge of SPIx_CLK Polarity 1 Phase 1 5 ns End of Table 7 68 Table 7 69 SPI Switching Characteristics Part 1 of 2 See Figure 7 38 and Figure 7 39 No Parameter Min Max Unit Master Mode Timing Diagr...

Page 201: ...K Polarity 1 Phase 0 2 P2 5 2 P2 5 ns 19 td SCS SPC Delay from SPIx_SCS active to first SPIx_CLK Polarity 1 Phase 1 0 5 tc 2 P2 5 0 5 tc 2 P2 5 ns 20 td SPC SCS Delay from final SPIx_CLK edge to maste...

Page 202: ...SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI MO 0 MO 1 MO n 1 MO n MI 0 MI 1 MI n 1 MI n MO 0 MO 1 MO n 1 MO n MI 0 MI 1 MI n 1 M...

Page 203: ...CMTXFLDAT Hold time MCMTXFLDAT valid after MCMTXFLCLK low 1 ns PM Interface 1 tc MCMRXPMCLK Clock period MCMRXPMCLK C3 5 75 ns 2 tw MCMRXPMCLK High pulse width MCMRXPMCLK 0 4 C3 0 6 C3 ns 3 tw MCMRXPM...

Page 204: ...rface that is being used PM or FL Figure 7 42 HyperLink Station Management Receive Timing xx represents the interface that is being used PM or FL 4 tosu MCMTXPMDAT MCMTXPMCLKL Setup time MCMTXPMDAT va...

Page 205: ...ata received from the DSP The DSP can read the UART status at any time The UART includes control capability and a processor interrupt system that can be tailored to minimize software management of the...

Page 206: ...ch as TCP and UDP ports It maintains 8k multiple in multiple out hardware queues It also provides checksum capability as well as some QoS capabilities It enables a single IP address to be used for a m...

Page 207: ...plex mode and 1000BaseT 1000 Mbps in full duplex mode with hardware flow control and quality of service QOS support The GbE switch subsystem is coupled with network coprocessor For more information se...

Page 208: ...66 for the register address and other details about the time synchronization module The register CPTS_RFTCLK_SEL for reference clock selection of time synchronization submodule is shown in Figure 7 4...

Page 209: ...signed to allow almost transparent operation of the MDIO interface with very little attention from the CorePac For more information see the Gigabit Ethernet GbE Switch Subsystem for KeyStone Devices U...

Page 210: ...he timer pins TINPLx and TOUTLx are connected to the low counter The timer pins TINPHx and TOUTHx are connected to the high counter When operating in watchdog mode the timer counts down to 0 and gener...

Page 211: ...aint lengths 5 6 7 8 and 9 Programmable encoder polynomials Programmable reliability and convergence lengths Hard and soft decoded decisions Tail and convergent modes Yamamoto logic Tail biting logic...

Page 212: ...iding connectivity and control among the components RapidIO is based on the memory and device addressing concepts of processor buses in which the transaction processing is managed completely by hardwa...

Page 213: ...ee an interrupt notifies the CPU that it is available 7 30 Antenna Interface Subsystem 2 AIF2 The enhanced Antenna Interface subsystem AIF2 consists of the Antenna Interface module and two SerDes macr...

Page 214: ...e RP1FBN valid before RP1CLKP high 2 ns 8 tsu RP1FBN RP1CLKN Setup time RP1FBN valid before RP1CLKN low 2 ns 8 tsu RP1FBN RP1CLKP Setup time RP1FBP valid before RP1CLKP high 2 ns 8 tsu RP1FBN RP1CLKN...

Page 215: ...everal components Two GCCP accelerators for finger despread FD path monitor PM preamble detection PD and stream power estimator SPE Back end interface BEI for management of the RAC configuration and t...

Page 216: ...event triggering AET This capability can be used to debug complex problems as well as understand performance characteristics of user applications AET provides the following capabilities Hardware prog...

Page 217: ...he 5 baseline JTAG signals e g no EMU 1 0 required for boundary scan Most interfaces on the device follow the Boundary Scan Test Specification IEEE1149 1 while all of the SerDes SRIO and SGMII support...

Page 218: ...TRST When using this type of JTAG controller assert TRST to initialize the DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations 7 34 3 2 JTAG El...

Page 219: ...as the content was not relevant Page 109 Added more description to Boot Sequence section Page 29 Changed all footnote references from CORECLK to SYSCLK1 Page 212 Corrected the typo in the address of M...

Page 220: ...ster Page 73 Added Setup and Hold times for RP1CLK and RP1CLK signals Page 213 Corrected the size of TETBs for the 4 cores from 16k to 4k Page 26 Added RSV0A and RSV0B pins to the Terminal list table...

Page 221: ...e thermal resistance characteristics for the PBGA CYP mechanical package B 2 Packaging Information The following packaging information reflects the most current released data available for the designa...

Page 222: ...TIVE FCBGA CYP 841 44 Green RoHS no Sb Br SNAGCU Level 4 245C 72HR 0 to 85 TMS320C6670XCYP 2010 TI 1 2GHZ TMS320C6670AXCYPA ACTIVE FCBGA CYP 841 44 Green RoHS no Sb Br SNAGCU Level 4 245C 72HR 40 to 1...

Page 223: ...in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exem...

Page 224: ...ng or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available f...

Page 225: ......

Page 226: ...sponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related inf...

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